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US4392124A
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Analog-digital coder comprising a charge transfer coded voltage generation
Assignee: Thales SA
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Filing: 1981-04-21
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Granted: 1983-07-05
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Expires: 2001-04-21
Abstract
Abstract This analog-ditigal coder determines the coefficients a o . . . a n in two stages: during the first stage, the generator processes voltages V R and V Ri with i=1 to k-1; during the second stage, the generator processes the voltages V R and V Ri with i=1 to n-k. A capacitive voltage divider (2 k C, C) preceded by two sample and hold means (S 3 , C 3 , S 4 , C 4 ) assures the division by 2 k of the voltages processed during the second stage and their summation with the final voltage V R (k-1) produced during the first stage.
Inventors
- 👤 Roger Benoit-Gonin
- 👤 Jean L. Berger
- 👤 Jean L. Coutures
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:45
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
139 words
An analog-digital coder comprising charge transfer coded voltage generator means for determining by successive approximations coefficients ao . . . an, equal to 0 or 1 of an analog voltage Vx to be coded with said analog voltage Vx coded in the form ##EQU4## in which VR is a reference voltage; said generator means including means for carrying out said coding in two stages, said carrying out means during the first stage for processing the voltages VR and VRi, ##EQU5## with i=1 to k, and k is approximately =(n+1)/2; said carrying out means for processing during the second stage for processing the voltages VR and VRi with i=n to (n-k), means for dividing by 2 k the processed voltages and for summing said second processed and divided voltages with the final voltage VR (k-1) produced during the first stage.
Claim 2
Dependent Claim
139 words
An analog-digital coder comprising charge transfer coded voltage generator means for determining by successive approximations coefficients ao . . . an, equal to 0 or 1 of an analog voltage Vx to be coded with said analog voltage Vx coded in the form ##EQU4## in which VR is a reference voltage; said generator means including means for carrying out said coding in two stages, said carrying out means during the first stage for processing the voltages VR and VRi, ##EQU5## with i=1 to k, and k is approximately =(n+1)/2; said carrying out means for processing during the second stage for processing the voltages VR and VRi with i=n to (n-k), means for dividing by 2 k the processed voltages and for summing said second processed and divided voltages with the final voltage VR (k-1) produced during the first stage.
Claim 3
Dependent Claim
109 words
A coder according to claim 1, wherein the said means are constituted by two sample and hold means (S 3 , C 3 , S 4 , C 4 ) and a two-channel capacitive voltage divider, each channel being connected to one of the sample and hold circuits, one of the channels comprising a capacitor of value 2 k C, while the other channel comprises a capacitor of value C, the voltages processed by the generator during the first stage being transmitted to the capacitor of value 2 k C, whilst the voltages processed by the generator during the second stage are transmitted to the capacitor of value C.
Claim 4
Dependent Claim
28 words
A coder according to claim 2, wherein the generator means comprises a charge reading device (CRD) which supplies voltages -V R and V Ri with i=1 to n.
Claim 5
Dependent Claim
34 words
A coder according to claim 3, wherein the output of the capacitive divider is connected to the output of a device to reverse the polarity of the voltage to be coded V x .
Claim 6
Dependent Claim
48 words
A coder according to claim 4, comprising a comparator with two inputs e 1 and e 2 , which supplies a 1 if the voltage applied to its input e 1 is greater than that applied to its input e 2 and a 0 in the opposite case.
Claim 7
Dependent Claim
70 words
A coder according to claim 5, wherein each input of the comparator is preceded by a sample and hold means (S 5 , C 5 , S 6 , C 6 ), said sample and hold means having a common point connected to the output of a follow-up stage (A), whose input is connected at the common point (Q) to the outputs of the capacitive divider and the reversing device.
Claim 8
Dependent Claim
14 words
A coder according to claim 6, wherein it is constructed according to MOS technology.
Claim 9
Dependent Claim
103 words
A coder according to claim 6 comprising means for determination of a sign bit a S of the voltage V x ; said determination taking place in two stages: during the first stage, the capacitor (C 6 ) of the sample and hold means (S 6 , C 6 ) connected to the input e 1 of the comparator is charged with the offset voltages of the different circuits; and during the second stage, voltage V x charges capacitor (C 5 ) of the sample and hold means (S 5 , C 5 ) connected to the input e 2 of the comparator.
Claim 10
Dependent Claim
89 words
A coder according to claim 8, wherein the coefficients a o . . . a n being determined by the comparator, and the capacitor (C 5 ) of the sample and hold means (S 5 , C 5 ) connected to the input e 1 of the comparator is charged by the voltage |V x |-V Ri and capacitor (C 6 ) of the sample and hold means (S 6 , C 6 ) connected to the input e 2 of the comparator is charged by the offset voltages.
Claim 11
Dependent Claim
17 words
A coder according to claim 9, being constructed in accordance with MOS technology with a buried channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-04 | 1987-01-03 | 1987-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-04 | 1991-01-03 | 1991-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-04 | 1995-01-03 | 1995-07-05 | $7700.00 | Window Closed / Lapsed |