Abstract This disclosure relates to a system and method for realizing asynchronous sequential circuits in a manner analagous to the stored state method for synchronous sequential circuits. The circuit is a stored state circuit including a memory and an output register with an input line and an input request line coupled to the memory and the output register having an output data line and an output acknowledge line. A pulse generator is coupled to the input request line so as to generate a timing signal, for transmission to the output register, a fixed period of time after receipt of a request signal on the input request line. A request signal will not appear on the input request line until a data signal on the input data line has stabilized. Furthermore, an acknowledge signal will not be generated until a signal on the output data line has stabilized. In this manner, an asynchronous sequential circuit is constructed which allows for utilization of existing component parts and provides for hazard-free and race-free implementations.
An asynchronous binary circuit comprising: a stored state circuit cell including a memory containing a state table of sets of state variables and an output register coupled to said memory to receive a current set of state variables; said cell having a source input data line and a source request line coupled to said memory, said output register having output lines; said output register being coupled to the input of said memory to address said memory along with said input data to fetch the next set of state variables; and a pulse generator coupled to said source request line and having a timing line coupled to said output register, said pulse generator including delay means to delay the transmission of a timing signal to said output register a fixed period of time after the receipt of a binary signal transition on said source request line.
Claim 2
Dependent Claim
145 words
An asynchronous binary circuit comprising: a stored state circuit cell including a memory containing a state table of sets of state variables and an output register coupled to said memory to receive a current set of state variables; said cell having a source input data line and a source request line coupled to said memory, said output register having output lines; said output register being coupled to the input of said memory to address said memory along with said input data to fetch the next set of state variables; and a pulse generator coupled to said source request line and having a timing line coupled to said output register, said pulse generator including delay means to delay the transmission of a timing signal to said output register a fixed period of time after the receipt of a binary signal transition on said source request line.
Claim 3
Dependent Claim
68 words
An asynchronous circuit according to claim 1 wherein: said output register contains output data; and said output lines further include a source output data line and a source acknowledge line, a destination request line and a destination output data line, said destination request line including delay means to delay the transmission of a destination request signal until there is a data signal on said destination output data line.
Claim 4
Dependent Claim
36 words
An asynchronous circuit according to claim 2 wherein: said source acknowledge line includes delay means to delay the transmission of said source acknowledge signal until there is a data signal on said source output data line.
Claim 5
Dependent Claim
40 words
An asynchronous circuit according to claim 3 wherein: said source input data line is provided with a transmission gate coupled to said memory cell; said source transmission gate being coupled to said source request line and said source acknowledge line.