Test unit for a logic circuit analyzer

Claim 2

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a scope signal input and a scope triggering input, said unit comprising: (a) a plurality of test probes being connectable to the plurality of test points to sense the output signals, respectively; (b) means for producing summed signals; (c) a plurality of impedance elements having different weighted values, each of said impedance elements being connected between one of said test probes and said producing means; (d) means for coupling the summed signals to the scope signal input; (e) means for selectively coupling and decoupling said test probes from said producing means; and (f) means for supplying a triggering signal to the scope triggering input in response to one of the sensed output signals.

Claim 3

A test unit according to claim 1 wherein said means for selectively coupling and decoupling comprises a plurality of switches, each being connected between one of said test probes and said producing means.

Claim 4

A test unit according to claim 2 wherein said plurality of switches are manual.

Claim 5

A test unit according to claim 1 wherein said means for supplying comprises means for selectively coupling one of the sensed output signals to the scope triggering input.

Claim 6

A test unit according to claim 4 wherein said means for selectively coupling one of the sensed output signals comprises a switch having a plurality of positions for connection to said test probes, respectively.

Claim 7

A test unit according to claim 1 further comprising means for receiving a signal external of the logic circuit, said means for supplying being constructed to supply the external signal to the scope triggering input.

Claim 8

A test unit according to claim 6 wherein said means for receiving the external signal comprises means for selectively delaying or not delaying the external signal.

Claim 9

A test unit according to claim 1 wherein said means for producing comprises a summing junction.

Claim 10

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a scope signal input and a scope triggering input, said unit comprising: (a) a plurality of test probes being connectable to the plurality of test points to sense the output signals, respectively; (b) means, having a summing junction, for producing summed signals; (c) a plurality of resistors having different weighted values, each of said resistors being connected between one of said test probes and said summing junction; (d) a plurality of first switches being connected between said test probes and said resistors, respectively, said first switches having one position coupling said test probes to said summing junction and another position decoupling said test probes from said summing junction; (e) a second switch having a plurality of selective positions and being connected to one of said test probes when in one of said plurality of selective positions to couple one of the sensed output signals to the scope triggering input; and (f) means for conducting the summed signals to the scope signal input.

Claim 11

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a scope signal input and a scope triggering input, said unit comprising: (a) a plurality of test probes being connectable to the plurality of test points to sense the output signals, respectively; (b) means, having a summing junction, for producing summed signals; (c) a plurality of resistors having different weighted values, each of said resistors being connected between one of said test probes and said summing junction; (d) a plurality of first switches being connected between said test probes and said resistors, respectively, said first switches having one position coupling said test probes to said summing junction and another position decoupling said test probes from said summing junction; (e) a second switch having a plurality of selective positions and being connected to one of said test probes when in one of said plurality of selective positions to couple one of the sensed output signals to the scope triggering input; and (f) means for conducting the summed signals to the scope signal input.

Claim 12

A test unit according to claim 9 further comprising: (a) means for receiving a signal external of the logic circuit; and (b) means for conducting the external signal either delayed or undelayed, said second switch having additional positions to couple the external signal delayed or undelayed to the scope triggering input.

Claim 13

A test unit according to claim 10 wherein said means for conducting the external signal comprises: (a) a first delay line having an adjustable delay; and (b) a second line without a delay.

Claim 14

A test unit according to claim 9 further comprising an additional pair of probes being connectable to the logic circuit to supply power for the test unit from the logic circuit.

Claim 15

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a first scope signal input, a second scope signal input and a scope triggering input, comprising: (a) a first set of a plurality of first test probes being connectable to a first set of the plurality of test points to sense the output signals; (b) first means, having a first summing junction, for producing first summed signals; (c) a first plurality of first impedance elements having different weighted values, each of said first impedance elements being connected between one of said first test probes and said first summing junction; (d) a plurality of first switches being connected between said first test probes and said first impedance elements, respectively, said first switches having one position coupling said first test probes to said first summing junction and another position decoupling said first test probes from said first summing junction; (e) first means for conducting the first summed signals to the first scope signal input; (f) a second set of a plurality of second test probes being connectable to a second set of the plurality of test points to sense the output signals; (g) second means, having a second summing junction, for producing second summed signals; (h) a second plurality of second impedance elements having different weighted values, each of said second impedance elements being connected between one of said second test probes and said second summing junction; (i) a plurality of second switches being connected between said second test probes and said second impedance elements, respectively, said second switches having one position coupling said second test probes to said second summing junction and another position decoupling said second test probes from said second summing junction; (j) second means for conducting the second summed signals to the second scope signal input; (k) a comparator having a first input, a second input and an output; (l) means for coupling the sensed output signals of said test probes to said first input of said comparator; (m) means for selectively generating and for coupling a predetermined logic reference signal to said second input of said comparator; (n) means for receiving a signal external of the logic circuit; (o) a first delay line for carrying the external signal; (p) a second line having no delay for carrying the external signal; and (q) switch means for selectively connecting any one of said first test probes, said second test probes, said output of said comparator, said first delay line or said second line to the scope triggering input.

Claim 16

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a first scope signal input, a second scope signal input and a scope triggering input, comprising: (a) a first set of a plurality of first test probes being connectable to a first set of the plurality of test points to sense the output signals; (b) first means, having a first summing junction, for producing first summed signals; (c) a first plurality of first impedance elements having different weighted values, each of said first impedance elements being connected between one of said first test probes and said first summing junction; (d) a plurality of first switches being connected between said first test probes and said first impedance elements, respectively, said first switches having one position coupling said first test probes to said first summing junction and another position decoupling said first test probes from said first summing junction; (e) first means for conducting the first summed signals to the first scope signal input; (f) a second set of a plurality of second test probes being connectable to a second set of the plurality of test points to sense the output signals; (g) second means, having a second summing junction, for producing second summed signals; (h) a second plurality of second impedance elements having different weighted values, each of said second impedance elements being connected between one of said second test probes and said second summing junction; (i) a plurality of second switches being connected between said second test probes and said second impedance elements, respectively, said second switches having one position coupling said second test probes to said second summing junction and another position decoupling said second test probes from said second summing junction; (j) second means for conducting the second summed signals to the second scope signal input; (k) a comparator having a first input, a second input and an output; (l) means for coupling the sensed output signals of said test probes to said first input of said comparator; (m) means for selectively generating and for coupling a predetermined logic reference signal to said second input of said comparator; (n) means for receiving a signal external of the logic circuit; (o) a first delay line for carrying the external signal; (p) a second line having no delay for carrying the external signal; and (q) switch means for selectively connecting any one of said first test probes, said second test probes, said output of said comparator, said first delay line or said second line to the scope triggering input.

Claim 17

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a scope signal input and a scope triggering input, comprising: (a) a plurality of test probes being connectable to a plurality of test points to sense the output signals; (b) a memory; (c) means for writing the output signals into and for reading the output signals from said memory; (d) means for producing weighted summed signals in response to the output signals from said test probes; (e) first switch means for coupling the output signals read from said memory or the weighted summed signals to the scope signal input; (f) means for providing and for coupling therethrough a first signal in response to at least one of the output signals from said test probes, said means for writing and for reading being responsive to the first signal to generate a second signal; and (g) second switch means for coupling the first signal or the second signal to the scope triggering input.

Claim 18

A test unit for identifying output signals at a plurality of test points of a logic circuit on an oscilloscope having a scope signal input and a scope triggering input, comprising: (a) a plurality of test probes being connectable to a plurality of test points to sense the output signals; (b) a memory; (c) means for writing the output signals into and for reading the output signals from said memory; (d) means for producing weighted summed signals in response to the output signals from said test probes; (e) first switch means for coupling the output signals read from said memory or the weighted summed signals to the scope signal input; (f) means for providing and for coupling therethrough a first signal in response to at least one of the output signals from said test probes, said means for writing and for reading being responsive to the first signal to generate a second signal; and (g) second switch means for coupling the first signal or the second signal to the scope triggering input.

Claim 19

A test unit according to claim 14 wherein said means for writing and for reading comprises selectable means, responsive to the first signal, for reading from said memory the output signals written into said memory before the occurrence of the signal or the output signals written into said memory after the occurrence of the first signal.

Claim 20

A test unit according to claim 14 wherein said means for writing and for reading comprises: (a) clock generator means for producing an internally generated write clock and an internally generated read clock; (b) means for selecting either the internally generated write clock or the internally generated read clock; and (c) means for addressing said memory in response to the selected internally generated write clock or the internally generated read clock.

Claim 21

A test unit according to claim 16 wherein said clock generator means includes means for adjusting the frequency of the internally generated write clock.

Claim 22

A test unit according to claim 17 further comprising means for displaying the internally generated write clock on the oscillocope.

Claim 23

A test unit according to claim 14 wherein said means for writing and for reading comprises: (a) a clock generator, having a write clock output and a clock input, for producing an internally generated write clock; and (b) means for switching said clock generator to couple an external clock on said clock input onto said write clock output or the internally generated write clock onto said clock output.

Claim 24

A test unit according to claim 14 further comprising means for delaying the second signal to said second switch means.

Claim 25

A test unit according to claim 14 wherein said means for providing and for coupling comprises: (a) a comparator having a first input, a second input and an output; (b) means for conducting the output signals from said test probes to said first input of said comparator; (c) means for selectively generating and for coupling a predetermined reference signal to said second input of said comparator; and (d) means for connecting said output of said comparator to said means for writing and for reading to couple the first signal thereto.

Claim 26

A test unit for identifying first output signals at a plurality of test points of a logic circuit on an oscilloscope having a first scope signal input, a second scope signal input and a scope triggering input, comprising: (a) a first set of a plurality of first test probes being connectable to a first set of the plurality of test points to sense the first output signals; (b) first means, selectively connected to said first test probes, for producing first, weighted, summed signals; (c) a second set of a plurality of second test probes being connectable to a second set of the plurality of test points to sense the first output signals; (d) second means, selectively connected to said second test probes, for producing second, weighted summed signals; (e) a memory; (f) means, connected to said first set and second set of test probes, for writing the first output signals into and for reading the first output signals from said memory; (g) first switch means for selectively coupling the first and second, weighted, summed signals to the first scope signal input and the second scope signal input or the first output signals read from said memory to the first scope signal input and the second scope signal input; (h) means for providing and for coupling therethrough a third signal in response to at least one of the first signals from said first set and said second set of test probes, said means for writing and for reading being responsive to the third signal to generate a fourth signal; and (i) second switch means for selectively coupling the third signal or the fourth signal to the scope triggering input.

Claim 27

A test unit for identifying first output signals at a plurality of test points of a logic circuit on an oscilloscope having a first scope signal input, a second scope signal input and a scope triggering input, comprising: (a) a first set of a plurality of first test probes being connectable to a first set of the plurality of test points to sense the first output signals; (b) first means, selectively connected to said first test probes, for producing first, weighted, summed signals; (c) a second set of a plurality of second test probes being connectable to a second set of the plurality of test points to sense the first output signals; (d) second means, selectively connected to said second test probes, for producing second, weighted summed signals; (e) a memory; (f) means, connected to said first set and second set of test probes, for writing the first output signals into and for reading the first output signals from said memory; (g) first switch means for selectively coupling the first and second, weighted, summed signals to the first scope signal input and the second scope signal input or the first output signals read from said memory to the first scope signal input and the second scope signal input; (h) means for providing and for coupling therethrough a third signal in response to at least one of the first signals from said first set and said second set of test probes, said means for writing and for reading being responsive to the third signal to generate a fourth signal; and (i) second switch means for selectively coupling the third signal or the fourth signal to the scope triggering input.