Pulse discriminator and misprobe detector for digital logic tester probe

Claim 2

A logic circuit tester probe system comprising: a high input impedance probe for making contact with a logic circuit node under test and producing in-phase signals in response to pulses at that node, said pulses having positive- and negative-going leading edges; impedance matching means coupled to the probe for receiving electrical signals therefrom; first means coupled to the impedance matching means for producing first signals in response to pulses having positive-going leading edges when the duration of the pulse is greater than a preselected value, and for producing first standby signals in response to pulses having negative-going leading edges; second means coupled to the impedance matching means for producing second signals in response to pulses having negative-going leading edges when the duration of the pulse is greater than the preselected value, and for producing second standby signals in response to pulses having positive-going leading edges; and output means coupled to the first and second means for rejecting pulses detected at the node having a duration less than the preselected value in response to the combination of the first signals and second standby signals or the second signals and the first standby signals.

Claim 3

A logic circuit tester probe system as in claim 1 wherein: the first means includes a first one-shot; the first signals have a duration approximately equal to the difference between the positive-going pulses detected at the circuit node and the duration of the output pulses of the first one-shot; the second means includes a second one-shot; and the second standby signals have a duration approximately equal to the sum of the duration of the positive-going pulses detected at the circuit node and the duration of the output pulses of the second one-shot.

Claim 4

A logic circuit tester probe system as in claim 1 wherein the preselected value is approximately 50 nanoseconds.

Claim 5

A logic circuit tester probe system as in claim 1 wherein: the first standby signals have a duration approximately equal to the sum of the duration of the negative-going pulses detected at the circuit node and the duration of the output pulses of the first one-shot; and the second signals have a duration approximately equal to the difference between the duration of the negative-going pulses detected at the circuit node and the duration of the negative pulses of the second one-shot.

Claim 6

A logic circuit tester probe system as in claim 1 further including misprobe detection means for determining whether the probe tip has made electrical contact with the circuit node under test, said detection means comprising: reference means coupled to the probe for providing a first reference voltage at the probe tip and for producing output signals in response to signals received at the probe tip; first comparator means having first and second inputs, of opposite phase relative to each other, said first input being coupled to a second reference voltage, and said second input being coupled to the reference means for producing an output signal at the output in response to an open circuit at the probe tip; and second comparator means having first and second inputs of opposite phase relative to each other, said first input being coupled to a third reference voltage and said second input being coupled to the reference means for producing an output signal in response to an open circuit at the probe tip; the relative phase of the output signals of the first and second comparator means being effective for indicating whether the probe tip has made electrical contact with the circuit node under test.

Claim 7

A logic circuit tester probe system as in claim 5 wherein the relative phase of the output signals of the first and the second comparator means is the same.

Claim 8

A logic circuit tester probe system as in claim 6 wherein the output signals of the first and second comparator means are both high level signals.

Claim 9

A logic circuit tester probe system as in claim 5 wherein the output signals of the first and second comparator means have first and second levels; and the first comparator means produces a first level output signal and the second comparator means produces a second level output signal in response to a voltage at the probe tip greater than the reference voltage.

Claim 10

A logic circuit tester probe system as in claim 8 wherein the first comparator means produces a second level output signal and the second comparator means produces a first level output signal in response to a voltage at the probe tip less than the first reference voltage.

Claim 11

A logic circuit tester probe system as in claim 9 wherein the first level of the output signal of the first and second comparator means is lower than the second level thereof.

Claim 12

A logic circuit tester probe system comprising: a high input impedance probe for making contact with a logic circuit node under test and producing in-phase signals in response to pulses detected at that node, said pulses having positive- and negative-going leading edges; impedance matching means coupled to the probe for receiving electrical signals therefrom; first means including a first one-shot coupled to the impedance matching means for producing first signals in response to pulses having positive-going leading edges, said first signals having a duration approximately equal to the difference between the duration of the positive-going pulses detected at the circuit node and the duration of output pulses of the first one-shot, and for producing first standby signals in response to pulses having negative-going leading edges; second means including a second one-shot coupled to the impedance matching means for producing second standby signals in response to pulses having postive-going leading edges, said second standby signals having a duration approximately equal to the sum of the duration of the positive-going pulses detected at the circuit node and the duration of the output pulses of the second one-shot, and for producing second signals in response to pulses having negative-going leading edges; and output means coupled to the first and second means for rejecting all pulses detected at the node having a duration less than the duration of the first signal in response to the combination of the first signals and the second standby signals or the second signals and the first standby signals.

Claim 13

A logic circuit tester probe system comprising: a high input impedance probe for making contact with a logic circuit node under test and producing in-phase signals in response to pulses detected at that node, said pulses having positive- and negative-going leading edges; impedance matching means coupled to the probe for receiving electrical signals therefrom; first means including a first one-shot coupled to the impedance matching means for producing first signals in response to pulses having positive-going leading edges, said first signals having a duration approximately equal to the difference between the duration of the positive-going pulses detected at the circuit node and the duration of output pulses of the first one-shot, and for producing first standby signals in response to pulses having negative-going leading edges; second means including a second one-shot coupled to the impedance matching means for producing second standby signals in response to pulses having postive-going leading edges, said second standby signals having a duration approximately equal to the sum of the duration of the positive-going pulses detected at the circuit node and the duration of the output pulses of the second one-shot, and for producing second signals in response to pulses having negative-going leading edges; and output means coupled to the first and second means for rejecting all pulses detected at the node having a duration less than the duration of the first signal in response to the combination of the first signals and the second standby signals or the second signals and the first standby signals.

Claim 14

A logic circuit tester probe system as in claim 11 wherein: the first standby signals have a duration approximately equal to the sum of the duration of the negative-going pulses detected at the circuit node and the duration of the output pulses of the first one-shot; and the second signals have a duration approximately equal to the difference between the duration of the negative-going pulses detected at the circuit node and the duration of the output pulses of the second one-shot.