Patent US4389705A successfully refreshed from Google Patents.
US4389705A
Expired / Lapsed
US
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Semiconductor memory circuit with depletion data transfer transistor
Assignee: STMicroelectronics lnc USA
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Filing: 1981-08-21
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Granted: 1983-06-21
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Expires: 2001-08-21
Abstract
Abstract A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14). The data transfer transistor ( 30) can be fabricated as a relatively small device due to the large turn on voltage applied thereto because the transistor (30) is a depletion device. The smaller size of a plurality of the transistors (30) results in a substantial saving in space and reduces capacitive loading on the data line (14) thereby speeding up the discharge rate of the data line (14).
Inventors
- 👤 Douglas P. Sheppard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
A semiconductor memory circuit, comprising: a word line connected to receive a first address signal; a column decode line connected to receive a second address signal; a bit line; a memory cell for storing a data state, said memory cell connected to be accessed by said first address signal received through said word line for driving said bit line to a voltage state corresponding to the data state stored in said memory cell; and a depletion data transfer transistor having the gate terminal thereof connected to said column decode line and the drain and source terminals thereof connected between said bit line and said data line for selectively connecting said bit line and said data line in response to said second address signal received through said column decode line.
Claim 2
Dependent Claim
129 words
A semiconductor memory circuit, comprising: a word line connected to receive a first address signal; a column decode line connected to receive a second address signal; a bit line; a memory cell for storing a data state, said memory cell connected to be accessed by said first address signal received through said word line for driving said bit line to a voltage state corresponding to the data state stored in said memory cell; and a depletion data transfer transistor having the gate terminal thereof connected to said column decode line and the drain and source terminals thereof connected between said bit line and said data line for selectively connecting said bit line and said data line in response to said second address signal received through said column decode line.
Claim 3
Dependent Claim
88 words
The semiconductor memory circuit recited in claim 1 wherein said memory cell comprises a read only memory (ROM) circuit having a memory transistor fabricated to have one of a plurality of threshold voltages, said memory transistor having the gate terminal thereof connected to said word line and the drain and source terminals thereof connected between said bit line and the drain terminal of a column select transistor having the gate terminal thereof connected to said column decode line and the source terminal thereof connected to a common node.
Claim 4
Dependent Claim
19 words
The semiconductor memory circuit recited in claim 1 including means for precharging said bit line and said data line.
Claim 5
Dependent Claim
223 words
A semiconductor memory circuit, comprising: a memory transistor fabricated to have one of a plurality of predetermined voltage thresholds corresponding to respective data states, the source and drain terminals of said memory transistor connected between a bit line and a first node; a word line connected to the gate terminal of said memory transistor, said word line for receiving a first address signal which has a first state when said word line is selected; a data line; means for precharging said bit line, said first node and said data line to said first state; a column decode line for receiving a second address signal which has a first state when said column line is selected; a depletion transistor having the gate terminal thereof connected to said column decode line and the drain and source terminals thereof connected between said bit line and said data line wherein said depletion transistor is rendered conductive when said second address signal is in said first state; and an enhancement transistor having the gate terminal thereof connected to said column decode line and the source and drain terminals thereof connected between a common node at a second state and said first node wherein said enhancement transistor is rendered conductive when said second address signal is in said first state thereby pulling said first node to said second state.
Claim 6
Dependent Claim
223 words
A semiconductor memory circuit, comprising: a memory transistor fabricated to have one of a plurality of predetermined voltage thresholds corresponding to respective data states, the source and drain terminals of said memory transistor connected between a bit line and a first node; a word line connected to the gate terminal of said memory transistor, said word line for receiving a first address signal which has a first state when said word line is selected; a data line; means for precharging said bit line, said first node and said data line to said first state; a column decode line for receiving a second address signal which has a first state when said column line is selected; a depletion transistor having the gate terminal thereof connected to said column decode line and the drain and source terminals thereof connected between said bit line and said data line wherein said depletion transistor is rendered conductive when said second address signal is in said first state; and an enhancement transistor having the gate terminal thereof connected to said column decode line and the source and drain terminals thereof connected between a common node at a second state and said first node wherein said enhancement transistor is rendered conductive when said second address signal is in said first state thereby pulling said first node to said second state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-20 | 1986-12-20 | 1987-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-20 | 1990-12-20 | 1991-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-20 | 1994-12-20 | 1995-06-21 | $7700.00 | Window Closed / Lapsed |