Patent US2415236A successfully refreshed from Google Patents.
Patent US4384400A successfully refreshed from Google Patents.
US4384400A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating monolithically interconnected series-parallel avalanche diodes
Assignee: United States Department of the Army
•
Filing: 1981-10-07
•
Granted: 1983-05-24
•
Expires: 2001-10-07
Abstract
Abstract Disclosed is an array of avalanche diodes and its method of manufacture which results in plural pairs of series connected mesa-etched avalanche (TRAPATT) diodes being selectively connected in parallel by metallized air bridges for increasing the impedance level and thereby the peak and average power level available from microwave oscillators and amplifiers configured therefrom. The various series connected diodes are placed in near proximity to respective neighboring diode pairs to reduce parasitics but at the same time the spacing is made sufficiently large to prevent thermal spreading of one diode pair to overlap that of the adjacent diode pair. The metallized air bridges in addition to providing a low inductance interconnection, provide an integrated heat capacitance which is necessary for high power operation.
Inventors
- 👤 Arye Rosen
- 👤 Jerome B. Klatskin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:44
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/01; H10W; H10W44/00; H10W44/20; H10W90/00; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7438
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
267 words
A method of forming an array of series-parallel monolithically interconnected TRAPATT avalanche diodes for increasing impedance levels for microwave oscillator and amplifier applications comprising the steps of: subjecting first and second selectively previously diffused like silicon wafers to a further diffusion; forming a metal contact surface on the upper, epitaxial surface of both said wafers; depositing a metallic substrate layer on the epitaxial surface of said first wafer contiguous with said contact surface previously formed thereon; reducing the thickness of said first wafer; forming a contact surface on the lower, sub-surface, of said first wafer thus reduced in thickness; bonding the epitaxial surface of said second wafer to the sub-surface of said first wafer via the respective contact surfaces and forming a metallic interface thereby; reducing the thickness of said second wafer forming a contact surface on the lower, sub-surface, of said second wafer thus reduced in thickness; defining the geometry of a plurality of diode sites on the sub-surface of said second wafer and applying a pattern of metallization at said diode sites; forming a first set of TRAPATT semiconductor diode mesas by mesa-etching steps upon said second silicon wafer at said diode sites; forming a second set of TRAPATT semiconductor diode mesas by mesa-etching steps upon said first silicon wafer at said diode sites directly beneath each mesa of said first set of diode mesas plural pairs of TRAPATT diode mesas connected in series in order to increase effective device impedance for peak power applications. forming metallized air bridge connections between selected pairs of series connected diode mesas for connecting said selected pairs in parallel.
Claim 2
Independent Claim
267 words
A method of forming an array of series-parallel monolithically interconnected TRAPATT avalanche diodes for increasing impedance levels for microwave oscillator and amplifier applications comprising the steps of: subjecting first and second selectively previously diffused like silicon wafers to a further diffusion; forming a metal contact surface on the upper, epitaxial surface of both said wafers; depositing a metallic substrate layer on the epitaxial surface of said first wafer contiguous with said contact surface previously formed thereon; reducing the thickness of said first wafer; forming a contact surface on the lower, sub-surface, of said first wafer thus reduced in thickness; bonding the epitaxial surface of said second wafer to the sub-surface of said first wafer via the respective contact surfaces and forming a metallic interface thereby; reducing the thickness of said second wafer forming a contact surface on the lower, sub-surface, of said second wafer thus reduced in thickness; defining the geometry of a plurality of diode sites on the sub-surface of said second wafer and applying a pattern of metallization at said diode sites; forming a first set of TRAPATT semiconductor diode mesas by mesa-etching steps upon said second silicon wafer at said diode sites; forming a second set of TRAPATT semiconductor diode mesas by mesa-etching steps upon said first silicon wafer at said diode sites directly beneath each mesa of said first set of diode mesas plural pairs of TRAPATT diode mesas connected in series in order to increase effective device impedance for peak power applications. forming metallized air bridge connections between selected pairs of series connected diode mesas for connecting said selected pairs in parallel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-23 | 1986-11-22 | 1987-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-23 | 1990-11-22 | 1991-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-23 | 1994-11-22 | 1995-05-24 | $7700.00 | Window Closed / Lapsed |