Method of making a metal programmable MOS read only memory device

Claim 1

A method of making a read-only memory comprising the steps of: forming a plurality of potential insulated gate field effect transistors without self-aligned gates in a face of a semiconductor body, each of the transistors having a source, a drain and a gate insulator but not a gate, the transistors being in a regular pattern of rows and columns to provide an array of memory cells, the columns being heavily-doped elongated regions in the face integral with the sources and drains and covered by thick oxide; forming a plurality of self-aligned silicon-gate transistors on said face peripheral to the array; applying a coating of conductive material over the face; and programming the array of memory cells by patterning the coating to define strips which provide the rows and to define extension of the strips out over the gate insulator for selected ones of the field effect transistors, said extensions providing the gates of said selected ones of the transistors, the remaining transistors having no such extensions being nonfunctional, wherein after the step of programming the face is ion implanted to raise the threshold of non-selected transistors in the array.

Claim 2

A method of making a read-only memory comprising the steps of: forming a plurality of potential insulated gate field effect transistors without self-aligned gates in a face of a semiconductor body, each of the transistors having a source, a drain and a gate insulator but not a gate, the transistors being in a regular pattern of rows and columns to provide an array of memory cells, the columns being heavily-doped elongated regions in the face integral with the sources and drains and covered by thick oxide; forming a plurality of self-aligned silicon-gate transistors on said face peripheral to the array; applying a coating of conductive material over the face; and programming the array of memory cells by patterning the coating to define strips which provide the rows and to define extension of the strips out over the gate insulator for selected ones of the field effect transistors, said extensions providing the gates of said selected ones of the transistors, the remaining transistors having no such extensions being nonfunctional, wherein after the step of programming the face is ion implanted to raise the threshold of non-selected transistors in the array.