High speed graphics

Claim 2

In a display device for displaying selected indicia on a field swept in a predetermined pattern apparatus for determining coordinates of an ellipse or degenerate forms thereof including: a processor for generating a sequence of digital signals, each representing a coordinate of said selected indicia in response to indicia selection signals, said processor comprising: initiating processor means responsive to said indicia selection signals for producing at least one signal representing a first coordinate and a further signal representing a rate of change of at least one component of said first coordinate, recursive processor means consisting essentially only of adders and shifters with an output of said recursive processor means coupled to an input and responsive to said at least one signal and to said further signal for producing a sequence of digital signals, each representing different coordinates of said selected indicia, each said different coordinates spaced from adjacent coordinates by a predetermined distance, and comparator means responsive to said signal sequences from said recursive processor means, and to signals indicative of instantaneous sweep position for illuminating said display field when said sweep is in a position corresponding to a coordinate of said indicia.

Claim 3

The apparatus of claim 1 in which said recursive processor means generates for each digital signal in said sequence representing a coordinate, a further digital signal representing rate of change of at least one component of said coordinate.

Claim 4

The apparatus of claim 2 wherein said recursive processor means includes at least one recursive processor, each said recursive processor including: a pair of shifting means, each with input and output, each for shifting digital signals provided at said input and producing shifted signals at said output, a pair of algebraic summing means, each with inputs and an output, for summing digital signals at said inputs to produce a summed signal at said output, and gating means for at times coupling said initiating processor means to said shifting means and for, at other times, coupling outputs of said pair of algebraic summing means to said shifting means.

Claim 5

The apparatus of claim 3 wherein: said pair of shifting means includes a first and second shifting means, each shifting an input by a predetermined and equal amount, said gating means comprises first and second gates, each with an output coupled respectively to first and second shifting means and wherein, said pair of algebraic summing means includes first and second adders with inputs of said first adder coupled to said first gate and said second shifting means and with inputs of said second adder coupled to said second gate and to said first shifting means, outputs of said first adder comprising said signal sequence, and wherein outputs of said first and second adders are connected to other inputs of said first and second gates, respectively.

Claim 6

The apparatus of claim 3 wherein said pair of shifting means includes: first and second shifting means, each including a prime shifting means and associated auxiliary shifting means, with an output of said prime shifting means connected to an input of an associated auxiliary shifting means, said gating means comprises first and second gates, each with an output coupled respectively to inputs of said prime shifting means, said pair of algebraic adders comprising first and second prime and auxiliary adders, each with two inputs and an output, inputs of said first prime adder connected to said first gating means and to said second prime shifting means, inputs of said first auxiliary adder connected to an output of said first prime adder, and to said first auxiliary shifting means, inputs of said second prime adder connected to said second gate and an output of said first prime shifting means, and said second auxiliary adder connected to said second prime adder and to said second auxiliary shifter means, outputs of said first auxiliary adder comprising said signal sequence, and wherein outputs of said first and second auxiliary adders are connected respectively to inputs of said first and second gates.

Claim 7

A display apparatus for displaying information bearing signals having a predetermined relationship with fixed indicia comprising means for generating signals indicative of said indicia, processor means responsive to said indicia indicating signals for producing in response to a gating signal a sequence of digital signals each representing different coordinates of said fixed indicia, a clock, two dimensional sweep means responsive to said clock for generating sweep signals for sweeping a display field in two dimensions, first gating means for gating said information bearing signals, visible signal generating means responsive to said sweep means and to said first gating means for generating visible signals corresponding to information bearing signals passed by said first gating means, first comparator means for comparing one of said indicia defining signals with a signal representing one coordinate of said instantaneous sweep position and for generating an output signal, second gating means responsive to said first comparator means for producing said gating signal for gating said processor means in response to an output signal from said first comparator means representing equal comparison, second comparator means responsive to an output of said processor means and to a signal representative of instantaneous sweep position in another coordinate for producing an output signal when said instantaneous sweep position signal bears a predetermined relation to an output of said processor means, means coupling said output signal of said second comparator means to said first gating means, wherein said processor means includes: initiating processor means responsive to said indicia indicating signals for producing intermediate signals, and recursive processor means responsive to said intermediate signals for generating said sequence of digital signals, whereby said processor means develops a sequence of digital signals describing said fixed indicia, and said second comparator means is conditioned to control said first gating means to pass only those information bearing signals which are represented by visible signals lying on a selected side of said fixed indicia.

Claim 8

A display apparatus for displaying information bearing signals having a predetermined relationship with fixed indicia comprising means for generating signals indicative of said indicia, processor means responsive to said indicia indicating signals for producing in response to a gating signal a sequence of digital signals each representing different coordinates of said fixed indicia, a clock, two dimensional sweep means responsive to said clock for generating sweep signals for sweeping a display field in two dimensions, first gating means for gating said information bearing signals, visible signal generating means responsive to said sweep means and to said first gating means for generating visible signals corresponding to information bearing signals passed by said first gating means, first comparator means for comparing one of said indicia defining signals with a signal representing one coordinate of said instantaneous sweep position and for generating an output signal, second gating means responsive to said first comparator means for producing said gating signal for gating said processor means in response to an output signal from said first comparator means representing equal comparison, second comparator means responsive to an output of said processor means and to a signal representative of instantaneous sweep position in another coordinate for producing an output signal when said instantaneous sweep position signal bears a predetermined relation to an output of said processor means, means coupling said output signal of said second comparator means to said first gating means, wherein said processor means includes: initiating processor means responsive to said indicia indicating signals for producing intermediate signals, and recursive processor means responsive to said intermediate signals for generating said sequence of digital signals, whereby said processor means develops a sequence of digital signals describing said fixed indicia, and said second comparator means is conditioned to control said first gating means to pass only those information bearing signals which are represented by visible signals lying on a selected side of said fixed indicia.

Claim 9

The apparatus of claim 6 in which said means for generating signals indicative of said indicia comprises storage means for storing signals indicative of an azimuth range for each said indicia and a radial length for end points of each said indicia at end points of said azimuth range, and in which said processor means includes, said initiating processor means for generating, in response to signals from storage means, said intermediate signals representing radius reciprocal and rate of change of radius reciprocal for at least one point on each said indicia.

Claim 10

The apparatus of claim 7 wherein said fixed indicia comprises first and second lines and said recursive storage means stores signals representing start and stop azimuths for said lines and radial length for said lines at said start and stop azimuth, said processor means further comprises first and second recursive processors responsive respectively to signals definitive of said first and second lines for producing first and second sequences of signals, each sequence representing coordinates on said first and second lines respectively, and in which said second comparator means produced said output signal if, and only if, said instantaneous sweep signal represents a coordinate lying between coordinates of said indicia represented by outputs of said first and second recursive processors.

Claim 11

The apparatus of claim 8 in which said sweep means produces an azimuth change signal and wherein said apparatus includes means coupling said azimuth change signal to said recursive processor means to control the rate at which said sequences of digital signals is produced.

Claim 12

The apparatus of claim 9 in which each said recursive processor means includes shifting means, for shifting a digital signal applied at an input, processor gating means for coupling either an output of said initiating processor means or an output of the recursive processor means to said shifting means input, and summing means responsive to outputs of said gating means and said shifting means and furnishing said output of said recursive processor means.

Claim 13

The apparatus of claim 9 wherein said processor gating means, shifting means and summing means each include a first processor gating means, first shifting means and first summing means for processing radius reciprocal representing signals and a second processor gating means, second shifting means and second summing means for processing rate of change radius reciprocal representing signals.