Code converter circuitry system for selectively rotating a video display picture

Claim 2

A code converter comprising in combination: (a) memory means for storing data signals at addressable locations therein; (b) a first address register for at least temporarily storing address representing signals; (c) a second address register having the output thereof coupled to said memory means; (d) control means; (e) an address rearranging circuit controlled by said control means and disposed between said first address register and said second address register for selectively transferring said address representing signals or a predetermined modification of said address representing signals to said second address register, said second address register being coupled to said memory means for selecting the data signals read out from said memory means; and (f) local code register means connected to the output of said memory means and to said control means for receiving the data signals read out from memory means and selectively supplying said data signals in a first order or a second order.

Claim 3

Apparatus as in claim 1 wherein said address rearranging circuit comprises: (a) a plurality of Exclusive OR gates, each having a first input connected to the output of said control means and a second input connected to the output of an individual stage of said first address register; (b) means coupling the output of predetermined ones of said plurality of Exclusive OR gates to the input of predetermined stages of said second address register; PG,24 (c) a plurality of binary adder circuits having a first input coupled to the output of other predetermined ones of said plurality of Exclusive OR gates, and a second input coupled to said control means; and (d) means coupling the output of said binary adder circuits to other predetermined stages of said second address register.

Claim 4

Apparatus as in claim 1 wherein said local code register means comprises: (a) a first multistage shift register having the input to its lowest order stage connected to the output of said memory means; (b) a second multistage shift register having the input to individual stages thereof coupled to the output of a corresponding stage of said first shift register and the output of individual stages thereof coupled to the inputs of corresponding stages of said first shift register; and (c) data selector means controlled by said control means for receiving the output of the highest order stage of said first shift register and the output of the lowest order stage of said second shift register.

Claim 5

Apparatus as in claim 3 and further including: (a) a cathode ray tube display device coupled to said data selector means.

Claim 6

Apparatus as in claim 4 wherein said cathode ray tube display device has a screen arbitrarily divided into a plurality of rectangular domains defined by horizontal scanning lines, X i , and vertical section lines, Y j , and wherein said memory means stores local codes representative of images to display in each of said plurality of domains.

Claim 7

Apparatus as in claim 5 wherein said address representing signal stored in first predetermined stages of said first address register define said section lines, Y j , and the address representing signals in second predetermined stages of said first address register define said scanning lines, X i .

Claim 8

Apparatus as in claim 6 wherein said address rearranging circuit receives said address representing signals from said first address register to form the signal set [X m ] and [Y n ] where [X m ]=[X i ]+[K 4 ] and [Y n ]=[Y j ]+[K 3 ] prior to transmission to said second address register.

Claim 9

Apparatus as in claim 7 wherein [K 4 ]=(00011111) 2 and [K 3 ]=0.

Claim 10

A code converting circuitry system for changing a first operating state wherein local codes of a first mode determined in correspondence with addressing codes and recorded in a memory are successively read out according to a first predetermined addressing sequence into a second operating state wherein local codes of the first mode are converted into local codes of a second mode according to a predetermined conversion rule and said local codes of the second mode are successively read out according to a second addressing sequence different from said first addressing sequence, comprising: (a) a changeover circuit for determining said first or second operating state; (b) a first address register which assigns addresses successively in said first addressing sequence; (c) an addressing sequence rearranging circuit controlled by said changeover circuit for transmitting the contents of said first address register without change or in a changed condition wherein said addressing codes are in said second addressing sequence; (d) a second address register for temporarily storing the output of said addressing sequence rearranging circuit; (e) a first local code register in which the local codes of said memory corresponding to the addresses indicated by said second address register are recorded and provided with an output to which the recorded local codes are supplied in the first mode; (f) a second local code register in which said local codes of said memory corresponding to the addresses indicated by said second address register are recorded and provided with an output to which the recorded local codes are supplied in the second mode; and (g) a data selector coupled to the output of said first and second local code registers for selecting and delivering the recorded codes of either said first or second local code register in response to the output of said changeover circuit.

Claim 11

A code converting circuitry system for changing a first operating state wherein local codes of a first mode determined in correspondence with addressing codes and recorded in a memory are successively read out according to a first predetermined addressing sequence into a second operating state wherein local codes of the first mode are converted into local codes of a second mode according to a predetermined conversion rule and said local codes of the second mode are successively read out according to a second addressing sequence different from said first addressing sequence, comprising: (a) a changeover circuit for determining said first or second operating state; (b) a first address register which assigns addresses successively in said first addressing sequence; (c) an addressing sequence rearranging circuit controlled by said changeover circuit for transmitting the contents of said first address register without change or in a changed condition wherein said addressing codes are in said second addressing sequence; (d) a second address register for temporarily storing the output of said addressing sequence rearranging circuit; (e) a first local code register in which the local codes of said memory corresponding to the addresses indicated by said second address register are recorded and provided with an output to which the recorded local codes are supplied in the first mode; (f) a second local code register in which said local codes of said memory corresponding to the addresses indicated by said second address register are recorded and provided with an output to which the recorded local codes are supplied in the second mode; and (g) a data selector coupled to the output of said first and second local code registers for selecting and delivering the recorded codes of either said first or second local code register in response to the output of said changeover circuit.

Claim 12

A code converting circuit as defined in claim 9, wherein said addressing sequence rearranging circuit is comprised of Exclusive OR gates which are disposed at respective bit stages of said first address register and which receive signals representative of states of the corresponding bits and the output from said changeover circuit.

Claim 13

A code converting circuit as in claim 9 wherein said addressing sequence rearranging circuit is comprised of Exclusive OR gates which are disposed at respective bit stages of said first address register and which receive signals representative of states of the corresponding bits and the output of said changeover circuit, and includes (a) adder means which receive outputs of said Exclusive OR gates and which add a desired constant thereto in response to the output of said changeover circuit or transfer them unaltered to said second address register.