Conic generator for on-the-fly digital television display

Claim 2

A video generator circuit for converting ordered data signals representing ellipses received from a data buffer into a time sequential video signal for use with a sequentially line scanned display device which displays a field composed of raster lines, wherein the improvement comprises: an input register connected to the output of said data buffer; decoding means connected to the output of said input register, for decoding said ordered data signals outputted from said data buffer and generating on a first output line components of the ellipse represented which lie along the display line to be scanned; modifying means having an input connected to the output of said input register, for modifying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said ellipse represented with the next display line to be scanned and outputting said modified data signal over an output line to an input line for storage in said data buffer; means connected to the output of said input register for inhibiting said outputting of said modified data signal when no components of said ellipse will intersect succeeding display lines to be scanned in said field.

Claim 3

The video generator circuit of claim 1, which further comprises: said raster lines having a vertical separation of ΔY; said ellipse being characterized by a display axis having an inverse slope ΔX p /ΔY and which intersects the vertical extrema of the ellipse and an inverse rate of change of the slope of the ellipse Δ 2 X q 2 /Δ 2 y ; said data signals including values for the constants ΔX p and Δ 2 X q 2 and values for X q 2 , ΔX q 2 and Xp at the extremum of said ellipse, where X q is the horizontal distance from said display axis to said ellipse.

Claim 4

The video generator circuit of claim 2, wherein: said input register comprises a first register means connected to the output of said data buffer for receiving values of ΔX p , Δ 2 X 2 q , X pn , X qn 2 , and ΔX 2 qn corresponding to an Nth one of said display lines; and said decoding means comprises: a square root generating means having an input connected to the output of said first register means for calculating the square root of X qn 2 ; a first adder means having an addend input connected to the output of said square root generator and an augend input connected to said first register means for calculating the sum X pn + X qn = X n and the difference X pn = X qn = X' n as the location along said Nth display line of the intersection with said ellipse; a second and a third register means connected to the output of said first adder means for storing the values of X n and X' n respectively; a second adder means having an addend input connected to the output of said square root generator and an augend input connected to said first register means for calculating the sum X pn +1 + X qn +1 = X' n +1 , and the difference X pn +1 - X qn +1 = X' n +1 as the location along said N+1st display line of the intersection with said ellipse; a forth and a fifth register means connected to the output of said second adder means for storing the values of X n -1 and X' n +1 respectively.

Claim 5

The video generator circuit of claim 3 wherein said square root generating means further comprises: a first shift register having a data input connected to said first register means; a read only memory having its memory address input connected to the high order n bits of said first shift register, for storing the square root of the number stored in said first shift register, rounded to the n most significant bits; a second shift register having a data input connected to the data output of said read only memory and an output connected to said first adder means, for receiving the value of the square root of the number stored in said first shift register rounded to the said n most significant bits; a control means connected to a control input of said first shift register and a control input of said second shift register; said control means shifting the contents of said first shift register two bits at a time for m times until a one bit occupies one of the two most significant bit positions of said first shift register, prior to accessing said read only memory with said shifted data therein; said control means shifting the contents of said second shift register one bit at a time for m times so that the accessed data occupies the least significant bit positions thereof; whereby the square root of X q 2 can be accessed in a minimum time with a minimum rounding error.

Claim 6

The video generator circuit of claim 3, wherein said modifying means further comprises: a third adder means having an augend and addend inputs connected to the output of said first register means and an output as a feedback to the input of said first register means to calculate the values of X q 2 n +1 = X q 2 n + ΔX 2 qn , ΔX 2 qn +1 = ΔX 2 qn + Δ 2 X 2 q and X pn +1 = X pn + ΔX p corresponding to the intersection of said ellipse with a line intermediate between the Nth and the N+1st ones of said display lines; said third adder means outputting the values of X 2 qn +1 and X pn +1 to the input of said first register means.

Claim 7

The video generator circuit of claim 5, wherein said decoding means further comprises: said square root generating means calculating the value of X qn +1 input from said first register means; a comparison means connected to said 2nd, 3rd, 4th and 5th register means to determine the larger value of X n or X n +1 and determine the larger value of X' n or X' n +1 ; a fourth adder means connected to said 2nd, 3rd, 4th and 5th register means and to said comparison means to calculate the origin the length of raster strokes along said Nth display line representing intersections with said ellipse; a video signal generating means having an input connected to said fourth adder means and an output connected to said display device for generating a video signal at the locations along said Nth display line corresponding to the intersection with said ellipse.

Claim 8

The video generator circuit of claim 2, wherein: said input register comprises a register means connected to the output of said data buffer for receiving values of ΔX p , Δ 2 X q 2 , Xp, Xq 2 and ΔX q 2 ; and said decoding means comprises square root generating means having an input connected to said register means for calculating the square root of X q 2 ; a first adder means having an addend input connected to the output of said square root generator and an augend input connected to said register means for calculating the sum X p + X q and the difference X p - X q as the location along said display line to be scanned of the intersection with said ellipse; a video signal generating means having an input connected to said first adder means and an output connected to a partial raster assembly storage, for generating a video signal at the locations along said display line to be scanned corresponding to said values of X p + X q and X p - X q .

Claim 9

The video generator circuit of claim 7 wherin said square root generating means further comprises: a first shift register having a data input connected to said register means; a read only memory having its memory address input connected to the high order n bits of said first shift register, for storing the square root of the number stored in said first shift register, rounded to the n most significant bits; a second shift register having a data input connected to the data output of said read only memory and an output connected to said first adder means for receiving the value of the square root of the number stored in said first shift register rounded to the said n most significant bits; a control means connected to a control input of said first shift register and a control input of said second shift register; said control means shifting the contents of said first shift register two bits at a time for m times until a one bit occupies one of the two most significant bit positions of said first shift register, prior to accessing said read only memory with said shifted data therein; said control means shifting the contents of said second shift register one bit at a time for m times so that the assessed data occupies the least significant bit positions thereof; whereby the square root of X q 2 can be accessed in a minimum time with a minimum rounding error.

Claim 10

The video generator circuit of claim 7, wherein said modifying means further comprises: a second adding means having augend and addend inputs connected to the output of said register means for adding ΔX p to X p to get a new value of X p , ΔX q 2 to X q 2 to get a new value of X q 2 , and Δ 2 X q 2 to ΔX 2 q to get a new value of ΔX q 2 and a sum output connected to the input of said register means; a data buffer output gate having an input connected to the output of said register means and an output of said modifying means output line connected to the input of said data buffer for rewriting said data word into said data buffer with said new values of X p , X q 2 and ΔX q 2 .

Claim 11

The video generator circuit of claim 2, wherein: said input register comprises a first register means connected to the output of said data buffer for receiving values of ΔX p , Δ 2 X 2 q , X pn , X qn 2 , and ΔX 2 qn corresponding to the Nth one of said display lines; and said decoding means comprises: a square root generating means having an input connected to the output of said first register means for calculating the square root of X qn 2 ; a first adder means having an addend input connected to the output of said square root generator and an augend input connected to said first register means for calculating the sum X pn + X qn = X n and the difference X pn - X qn = X' n as the location along said Nth display line of the intersection with said ellipse; a second and a third register means connected to the output of said first adder means for storing the values of X n and X' n respectively.

Claim 12

The video generator circuit of claim 10 wherein said square root generating means further comprises: a first shift register having a data input connected to said first register means; a read only memory having its memory address input connected to the high order n bits of said first shift register, for storing the square root of the number stored in said first shift register, rounded to the n most significant bits; a second shift register having a data input connected to the data output of said read only memory and an output connected to said first adder means for receiving the value of the square root of the number stored in said first shift register rounded to the said n most significant bits; a control means connected to a control input of said first shift register and a control input of said second shift register; said control means shifting the contents of said first shift register two bits at a time for m times until a one bit occupies one of the two most significant bit positions of said first shift register, prior to accessing said read only memory with said shifted data therein; said control means shifting the contents of said second shift register one bit at a time for m times so that the accessed data occupies the least significant bit positions thereof; whereby the square root of X q 2 can be accessed in a minimum time with a minimum rounding error.

Claim 13

The video generator circuit of claim 10, wherein said modifying means further comprises: a second adder means having an augend and addend inputs connected to the output of said first register means and an output as a feedback to the input of said first register means to calculate the values of X q 2 n +1 = X q 2 n + ΔX 2 qn , ΔX 2 qn +1 = ΔX 2 qn + Δ 2 X 2 q and X pn +1 = X pn + ΔX p corresponding to the intersection of said ellipse with a line intermediate between the Nth and the N+1st ones of said display lines; said second adder means outputting the values of X 2 qn +1 and X pn +1 to the input of said first register means; said square root generating means of said decoding means calculating the value of X qn +1 input from said register means; said first adder means of said decoding means calculating the sum of X pn +1 + X qn +1 = X n +1 and the difference X pn +1 - X qn +1 + X' n +1 as the location along said line midway between said Nth and said N+1st display lines of the intersection with said ellipse.

Claim 14

The video generator circuit of claim 12, wherein said decoding means further comprises: a fourth and a fifth register means connected to the output of said first adder means for storing the values of X n +1 and X' n +1 , respectively; a comparison means connected to said 2nd, 3rd, 4th and 5th register means to determine the larger value of X n or X n +1 and determine the larger value of X' n or X' n +1 ; a third adder means connected to said 2nd, 3rd, 4th and 5th register means and to said comparison means to calculate the origin and length of raster strokes along with Nth display line representing intersections with said ellipse.

Claim 15

The video generation circuit of claim 13, which further comprises: a video signal generating means having an input connected to said third adder means and an output connected to said display device for generating a video signal at the locations along said Nth display line corresponding to the intersection with said ellipse.

Claim 16

A video generator circuit for converting randomly occurring data signals representing ellipses received from a host processor into a time sequential video signal for use with a sequentially line scanned display device which displays a field composed of raster lines, wherein the improvement comprises, in combination: an ordered refresh buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line position for the ellipse represented; an intermediate buffer having a first input connected to the output of said ordered refresh buffer for storing said ordered data signals once during each display field before the display of the ellipse represented and outputting said ordered data signals in synchronism with the line scan of the display; a conic generator means which includes an input register connected to the output of said intermediate buffer and a decoding means connected to the output of said input register for decoding said ordered data signals outputted from said intermediate buffer and generating on an output line components of the ellipse represented which lie along the display line to be scanned; a partial raster assembly storage connected to said output line from said decoding means of said conic generator means, to store the components of the ellipse represented which lie along the display line to be scanned; said conic generator means further including a modifying means connected to the output of said input register, for modifying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said ellipse represented with the next display line to be scanned, and outputting said modified data signal to a second input line for storage in said intermediate buffer; said conic generator means including means connected to the output of said input register to inhibit the output of a modified data signal to said intermediate buffer when no components of said ellipse will intersect succeeding display lines to be scanned in said field.

Claim 17

A video generator circuit for converting randomly occurring data signals representing ellipses received from a host processor into a time sequential video signal for use with a sequentially line scanned display device which displays a field composed of raster lines, wherein the improvement comprises, in combination: an ordered refresh buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line position for the ellipse represented; an intermediate buffer having a first input connected to the output of said ordered refresh buffer for storing said ordered data signals once during each display field before the display of the ellipse represented and outputting said ordered data signals in synchronism with the line scan of the display; a conic generator means which includes an input register connected to the output of said intermediate buffer and a decoding means connected to the output of said input register for decoding said ordered data signals outputted from said intermediate buffer and generating on an output line components of the ellipse represented which lie along the display line to be scanned; a partial raster assembly storage connected to said output line from said decoding means of said conic generator means, to store the components of the ellipse represented which lie along the display line to be scanned; said conic generator means further including a modifying means connected to the output of said input register, for modifying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said ellipse represented with the next display line to be scanned, and outputting said modified data signal to a second input line for storage in said intermediate buffer; said conic generator means including means connected to the output of said input register to inhibit the output of a modified data signal to said intermediate buffer when no components of said ellipse will intersect succeeding display lines to be scanned in said field.

Claim 18

The video generator circuit of claim 9, which further comprises: said raster lines having a vertical separation of Δy; said ellipse being characterized by a display axis having an inverse slope ΔX p /Δy and which intersects the vertical extrema of the ellipse and an inverse rate of change of the slope of the ellipse Δ 2 X q 2 /Δ 2 y; said data signals including values for the constants ΔXp and Δ 2 X q 2 and values for X q 2 , ΔX q 2 and Xp at the extremum of said ellipse, where X q is the horizontal distance from said display axis to said ellipse.

Claim 19

The video generator circuit of claim 16, wherein: said input register comprises a register means connected to the output of said data buffer for receiving values of ΔX p , Δ 2 X q 2 , X p , X q 2 and ΔX q 2 ; and said decoding means further comprises: square root generating means having an input connected to said register means for calculating the square root of X q 2 ; a first adder means having an addend input connected to the output of said square root generator and an augend input connected to said register means for calculating the sum X p + X q and the difference X p - X q as the location along said display line to be scanned of the intersection with said ellipse; a video signal generating means having an input connected to said first adder means and an output connected to a partial raster assembly storage, for generating a video signal at the locations along said display line to be scanned corresponding to said values of X p + X q and X p - X q .

Claim 20

The video generator circuit of claim 17, wherein said square root generating means further comprises: a first shift register having a data input connected to said register means; a read only memory having its memory address input connected to the high order n bits of said first shift register, for storing the square root of the number stored in said first shift register, rounded to the n most significant bits; a second shift register having a data input connected to the data output of said read only memory and an output connected to said first adder means for receiving the value of the square root of the number stored in said first shift register rounded to the said n most significant bits; a control means connected to a control input of said first shift register and a control input of said second shift register; said control means shifting the contents of said first shift register two bits at a time for m times until a one bit occupies one of the two most significant bit positions of said first shift register, prior to accessing said read only memory with said shifted data therein; said control means shifting the contents of said second shift register one bit at a time for m times so that the assessed data occupies the least significant bit positions thereof; whereby the square root of X q 2 can be accessed in a minimum time with a minimum rounding error.

Claim 21

The video generator circuit of claim 17, wherein said modifying means further comprises: a second adding means having augend and addend inputs connected to the output of said register means for adding ΔX p to X p to get a new value of X p , ΔX q 2 to X q 2 to get a new value of X q 2 , and Δ 2 X q 2 to ΔX 2 q to get a new value of ΔX q 2 and a sum output connected to the input of said register means; a data buffer output gate having an input connected to the output of said register means and an output connected to said second input of said intermediate buffer for rewriting said data word into said intermediate buffer with said new values for X p , X q 2 and ΔX q 2 .

Claim 22

The video generator circuit of claim 16, wherein: said input register comprises a first register means connected to the output of said data buffer for receiving values of ΔX p , Δ 2 X 2 q , X pn , X qn 2 , and ΔX 2 qn corresponding to an Nth one of said display lines; and said decoding means comprises: a square root generating means having an input connected to the output of said first register means for calculating the square root of X qn 2 ; a first adder means having an addend input connected to the output of said square root generator and an augend input connected to said first register means for calculating the sum X pn + X qn = X n and the difference X pn - X qn = X' n as the location along said Nth display line of the intersection with said ellipse; a second and a third register means connected to the output of said first adder means for storing the values of X n and X' n respectively.

Claim 23

The video generator circuit of claim 20 wherein said square root generating means further comprises: a first shift register having a data input connected to said first register means; a read only memory address input connected to the high order n bits of said first shift register, for storing the square root of the number stored in said first shift register, rounded to the n most significant bits; a second shift register having a data input connected to the data output of said read only memory and an output connected to said first adder means for receiving the value of the square root of the number stored in said first shift register rounded to the said n most significant bits; a control means connected to a control input of said first shift register and a control input of said second shift register; said control means shifting the contents of said first shift register two bits at a time for m times until a one bit occupies one of the two most significant bit positions of said first shift register, prior to accessing said read only memory with said shifted data therein; said control means shifting the contents of said second shift register one bit at a time for m times so that the accessed data occupies the least significant bit positions thereof; whereby the square root of X q 2 can be accessed in a minimum time with a minimum rounding error.

Claim 24

The video generator circuit of claim 20, wherein said modifying means further comprises: a second adder means having an augend and addend inputs connected to the output of said first register means and an output as a feedback to the input of said first register means to calculate the values of X q 2 n +1 = X q 2 n + ΔX 2 qn , ΔX 2 qn +1 = ΔX 2 qn + Δ 2 X 2 q and X pn +1 = X pn + ΔX p corresponding to the intersection of said ellipse with a line intermediate between the Nth and the N+1st ones of said display lines; said second adder means outputting the values of X 2 qn +1 and X pn +1 to the input of said first register means; said square root generating means of said decoding means calculating the value of X qn +1 from the value of X 2 qn +1 input from said first register means; said first adder means of said decoding means calculating the sum of X pn +1 + X qn +1 and the difference X pn +1 - X qn +1 = X' n +1 as the location along said line midway between said Nth and said N+1st display lines of the intersection with said ellipse.

Claim 25

The video generator circuit of claim 22, wherein said decoding means further comprises: a fourth and a fifth register means connected to the output of said first adder means for storing the values of X n +1 and X' n +1 , respectively; a comparison means connected to said 2nd, 3rd, 4th and 5th register means to determine the larger value of X n or X n +1 and determine the larger value of X' n or X' n +1 ; a third adder means connected to said 2nd, 3rd, 4th and 5th register means and to said comparison means to calculate the origin and length of raster strokes along said Nth display line representing intersections with said ellipse.

Claim 26

The video generator circuit of claim 23, which further comprises: a video signal generating means having an input connected to said third adder means and an output connected to said display device for generating a video signal at the locations along said Nth display line corresponding to the intersection with said ellipse.

Claim 27

The video generator circuit of claim 16, wherein: said input register comprises a first register means connected to the output of said data buffer for receiving values of ΔX p , Δ 2 X 2 q , X pn , X qn 2 , and ΔX 2 qn corresponding to an Nth one of said display lines; and said decoding means comprises: a square root generating means having an input connected to the output of said first register means for calculating the square root of X qn 2 ; a first adder means having an addend input connected to the output of said square root generator and an augend input connected to said first register means for calculating the sum X pn + X qn = X n and the difference X pn - X qn = X' n as the location along said Nth display line of the intersection with said ellipse; a second and a third register means connected to the output of said first adder means for storing the values of X n and X' n respectively; a second adder means having an addend input connected to the output of said square root generator and an augend input connected to said first register means for calculating the sum X pn +1 + X qn +1 = X n +1 and the difference X pn +1 - X qn +1 = X' n +1 as the location along said N+1st display line of the intersection with said ellipse; a fourth and a fifth register means connected to the output of said second adder means for storing the values of X n +1 and X' n +1 respectively.

Claim 28

The video generator circuit of claim 25 wherein said square root generating means further comprises: a first shift register having a data input connected to said first register means; a read only memory having its memory address input connected to the high order n bits of said first shift register, for storing the square root of the number stored in said first shift register, rounded to the n most significant bits; a second shift register having a data input connected to the data output of said read only memory and an output connected to said first adder means, for receiving the value of the square root of the number stored in said first shift register rounded to the said n most significant bits; a control means connected to a control input of said first shift register and a control input of said second shift register; said control means shifting the contents of said first shift register two bits at a time for m times until a one bit occupies one of the two most significant bit positions of said first shift register, prior to accessing said read only memory with said shifted data therein; said control means shifting the contents of said second shift register one bit at a time for m times so that the accessed data occupies the least significant bit positions thereof; whereby the square root of X q 2 can be accessed in a minimum time with a minimum rounding error.

Claim 29

The video generator circuit of claim 25, wherein said modifying means further comprises: a third adder means having an augend and addend inputs connected to the output of said first register means and an output as a feedback to the input of said first register means to calculate the values of X q 2 n +1 = X q 2 n + ΔX 2 qn , ΔX 2 qn +1 = ΔX 2 qn + Δ 2 X 2 q and X pn +1 = X pn + ΔX p corresponding to the intersection of said ellipse with a line intermediate between the Nth and the N+1st ones of said display lines; said third adder means outputting the values of X 2 qn +1 and X pn +1 to the input of said first register means.

Claim 30

The video generator circuit of claim 27, wherein said decoding means further comprises: said square root generating means calculating the value of X qn +1 input from said first register means; a comparison means connected to said 2nd, 3rd, 4th and 5th register means to determine the larger value of X n or X n +1 and determine the larger value of X' n or X' n +1 ; a fourth adder means connected to said 2nd, 3rd, 4th and 5th register means and to said comparison means to calculate the origin and length of raster strokes along said Nth display line representing intersections with said ellipse; a video signal generating means having an input connected to said fourth adder means and an output connected to said display device for generating a video signal at the locations along said Nth display line corresponding to the intersection with said ellipse.