Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
157 words
A circuit for determining the leading or lagging phase relationship between first and second two-level signals at each level transition of said first two-level signal, and comprising: first and second Exclusive OR gate means each having first input terminals for receiving said first and second two level signals respectively and further having a second input terminal and an output terminal; decoding means having first and second input terminals coupled respectively only to the output terminals of said first and second Exclusive OR gate means and responsive only to the level transitions of said first signal to detect the leading or lagging phase relationship of said first and second signals at said each level transition of said first signal, and to supply to the second input terminals of said first and second Exclusive OR gate means after each detection of said phase relationship a third signal having a level equal to the concurrent level of said first signal.
Claim 2
Dependent Claim
157 words
A circuit for determining the leading or lagging phase relationship between first and second two-level signals at each level transition of said first two-level signal, and comprising: first and second Exclusive OR gate means each having first input terminals for receiving said first and second two level signals respectively and further having a second input terminal and an output terminal; decoding means having first and second input terminals coupled respectively only to the output terminals of said first and second Exclusive OR gate means and responsive only to the level transitions of said first signal to detect the leading or lagging phase relationship of said first and second signals at said each level transition of said first signal, and to supply to the second input terminals of said first and second Exclusive OR gate means after each detection of said phase relationship a third signal having a level equal to the concurrent level of said first signal.
Claim 3
Dependent Claim
78 words
A circuit as in claim 1 in which said decoding means comprises: bi-directional counting means responsive to the output signals from said first and second Exclusive OR gate means to count up or down at each level transition of said first signal in accordance with the level of said output signal from said second Exclusive OR gate means and in which the contents of the least significant bit position of said bi-directional counting means comprises said third signal.
Claim 4
Dependent Claim
54 words
A circuit as in claim 1 in which said decoding means comprises: data processing means responsive to the output signals from said first and second Exclusive OR gate means for determining the phase relationship of said first and second signals at each level transition of said first signal and for generating said third signal.
Claim 5
Dependent Claim
192 words
A circuit for detecting leading or lagging phase relationship between first and second two level signals at each level transition of said first signal and comprising: first and second Exclusive OR gating means each having first and second input terminal means and output terminal means and each responsive to signals of equal and non-equal levels supplied to the first and second input terminal means thereof to produce on said output terminal means an output signal having a first and second level, respectively; first means for supplying said first and second signals to the first input terminal means of said first and second Exclusive OR gating means respectively; decoding means having first and second input terminals coupled respectively to the output signals of said first and second Exclusive OR gating means only to determine the phase relationship of said first and second signals at each level transition of said first signal only and for generating and supplying to said second input terminal means of said first and second Exclusive OR gating means after each determination of phase relationship a third signal whose level is equal to the concurrent level of said first signal.
Claim 6
Dependent Claim
192 words
A circuit for detecting leading or lagging phase relationship between first and second two level signals at each level transition of said first signal and comprising: first and second Exclusive OR gating means each having first and second input terminal means and output terminal means and each responsive to signals of equal and non-equal levels supplied to the first and second input terminal means thereof to produce on said output terminal means an output signal having a first and second level, respectively; first means for supplying said first and second signals to the first input terminal means of said first and second Exclusive OR gating means respectively; decoding means having first and second input terminals coupled respectively to the output signals of said first and second Exclusive OR gating means only to determine the phase relationship of said first and second signals at each level transition of said first signal only and for generating and supplying to said second input terminal means of said first and second Exclusive OR gating means after each determination of phase relationship a third signal whose level is equal to the concurrent level of said first signal.
Claim 7
Dependent Claim
55 words
A circuit as in claim 4 in which said decoding means comprises: data processing means responsive to the output signals from said first and second Exclusive OR gating means only for determining the phase relationship of said first and second signals at each level transition of said first signal and for generating said third signal.
Claim 8
Dependent Claim
78 words
A circuit as in claim 4 in which said decoding means comprises: bi-directional counting means responsive to the output signal from said first and second Exclusive OR gating means to count up or down at each level transition of said first signal in accordance with the level of said output signal from said second Exclusive OR gating means and in which the contents of the least significant bit position of said bi-directional counting means comprises said third signal.