Abstract A phase decoding technique is provided which, when applied to a pair of quadrature-phased digital-electronic signals (i.e. having a 90° phase relationship) such as those normally associated with incremental optical position encoders, produces signals suitable for incrementing or decrementing up-down counters in accordance with the phase relationship and pulse rate of these quadrature phased signals. This is accomplished through circuitry which is entirely of a digital nature and relys on comparisons of samples of the quadrature-phased signals which are taken and stored in a time-sequential manner. Since no analog circuitry is employed, the disadvantages of phase decoders using prior art techniques are avoided.
Inventors
👤 Robert Osann, Jr.
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-30 22:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
132 words
An electronic circuit for decoding rate and direction information from a pair of quadrature-phased electronic signals comprising: a square-wave oscillator for producing sampling pulses; first register means responsive to said quadrature-phased signals and to said sampling pulses for storing sampled states of said quadrature-phased electronic signals; second register means responsive to said first register means and said sampling pulses for storing the sampled states of said quadrature-phased signals which had been previously stored by said first register means; static memory means connected to perform a comparing operation on the outputs of said first and second register means; and digital logic means responsive to said static memory means and said sampling pulses providing appropriate signals for incrementing or decrementing an up/down counter means according to the comparison performed by said static memory means.
Claim 2
Dependent Claim
132 words
An electronic circuit for decoding rate and direction information from a pair of quadrature-phased electronic signals comprising: a square-wave oscillator for producing sampling pulses; first register means responsive to said quadrature-phased signals and to said sampling pulses for storing sampled states of said quadrature-phased electronic signals; second register means responsive to said first register means and said sampling pulses for storing the sampled states of said quadrature-phased signals which had been previously stored by said first register means; static memory means connected to perform a comparing operation on the outputs of said first and second register means; and digital logic means responsive to said static memory means and said sampling pulses providing appropriate signals for incrementing or decrementing an up/down counter means according to the comparison performed by said static memory means.