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US3729677A Expired / Lapsed US ⏱️ 0.0 years remaining

Gate control apparatus for setting the input signal counting interval

Assignee: HP Inc
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Filing: 1972-05-22
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Granted: 1973-04-24
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Expires: 1992-05-22
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Abstract

Abstract A decade counting and display assembly are combined with a reference frequency source, pulse shaper, gate control apparatus and conventional logic elements to provide a frequency measuring device that automatically determines a time interval during which the frequency of an input signal is counted. The same components are used to provide a multiperiod averaging device that automatically determines a number of periods an input signal is to be averaged.

Inventors

  • 👤 I Band

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 19:34
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; G01R23/10

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 793 words
Frequency measuring apparatus comprising: a plurality of selective timing means, each of which forms a single stage comprising: a. logic means to divide an input signal by B, having a reset input for setting said logic means to an initial state in response to a signal being applied thereto, a drive input for altering said initial state by one count in response to each signal pulse being applied thereto and having a first output for producing signals representing a number stored in said logic means, a second output for producing a true level signal in response to the logic means being in a first cycle of operation, a third output for producing a true level signal in response to said logic means being in the initial state and a carry output for producing a signal in response to a number B being stored in said logic means, wherein B is an integer greater than one (1) and said first cycle of operation begins upon a signal being applied to the reset input of said logic means and ends when a number B of signal pulses have been applied to the drive input of said logic means; b. decoder means having an input connected to the first output of said logic means and having an outpuT for producing a true level signal in response to a signal representing a number A appearing at said input, wherein A is an integer greater than zero (0) and less than or equal to B-1; c. first gating means having an input connected to the output of said decoder means, an input connected to the second output of said logic means and having an output for producing a true level signal in response to a number A being stored in said logic means during the first cycle of operation of said logic means; and d. second gating means having an input connected to the output of said first gating means, an input connected to the third output of said logic means and having an output for producing a true level signal in response to either the logic means being an initial state or a number A being stored in said logic means during said first cycle of operation; third gating means having a first input connected to the output of said second gating means and a second input and having a gated output for producing a signal at said output in response to true level signals at said first and second inputs; means connecting together the reset inputs of each stage to simultaneously set each stage to an initial state upon a signal being applied at any reset input; means connecting the drive input of a first stage to the second input of the third gating means of that first stage; means connecting the carry output of a preceding stage to the drive input of a succeeding stage; means connecting the gated output of the third gating means of a preceding stage to the second input of the third gating means of a succeeding stage for producing a signal at the gated output of a last stage of said gate control apparatus in response to AB0+ 1, AB1+ 1 . . . ABx 1+ 1 and nBx+ 1 signal pulses applied at the signal input of the first stage of said gate control apparatus, where x is an integer representing the number of stages in said gate control apparatus and n is an integer zero (0) or greater; a source of reference frequency signal pulses; decade counting and display means having an input and having an output responsive to the number of cycles a signal has been applied to said input for displaying said number in digitized form; switching means having an output connected to the input of said decade counting and display means and having a first input connected to receive an input signal to be counted, a second input and a third input connected to the gated output of the last stage of said gate control apparatus for connecting the input signal to be counted at said first input to the output of said switching means in response to a signal appearing at said third input of said switching means and for disconnecting said input signal to be counted from the output of said switching means in response to the first signal that appears at said third input after a signal has appeared at said second input; and means having an input connected to the output of said decade counting and display means and having an output connected to the second input of said signal switching means for producing a signal in response to a certain number being registered in said decade counting and display means.
Claim 2
Dependent Claim 793 words
Frequency measuring apparatus comprising: a plurality of selective timing means, each of which forms a single stage comprising: a. logic means to divide an input signal by B, having a reset input for setting said logic means to an initial state in response to a signal being applied thereto, a drive input for altering said initial state by one count in response to each signal pulse being applied thereto and having a first output for producing signals representing a number stored in said logic means, a second output for producing a true level signal in response to the logic means being in a first cycle of operation, a third output for producing a true level signal in response to said logic means being in the initial state and a carry output for producing a signal in response to a number B being stored in said logic means, wherein B is an integer greater than one (1) and said first cycle of operation begins upon a signal being applied to the reset input of said logic means and ends when a number B of signal pulses have been applied to the drive input of said logic means; b. decoder means having an input connected to the first output of said logic means and having an outpuT for producing a true level signal in response to a signal representing a number A appearing at said input, wherein A is an integer greater than zero (0) and less than or equal to B-1; c. first gating means having an input connected to the output of said decoder means, an input connected to the second output of said logic means and having an output for producing a true level signal in response to a number A being stored in said logic means during the first cycle of operation of said logic means; and d. second gating means having an input connected to the output of said first gating means, an input connected to the third output of said logic means and having an output for producing a true level signal in response to either the logic means being an initial state or a number A being stored in said logic means during said first cycle of operation; third gating means having a first input connected to the output of said second gating means and a second input and having a gated output for producing a signal at said output in response to true level signals at said first and second inputs; means connecting together the reset inputs of each stage to simultaneously set each stage to an initial state upon a signal being applied at any reset input; means connecting the drive input of a first stage to the second input of the third gating means of that first stage; means connecting the carry output of a preceding stage to the drive input of a succeeding stage; means connecting the gated output of the third gating means of a preceding stage to the second input of the third gating means of a succeeding stage for producing a signal at the gated output of a last stage of said gate control apparatus in response to AB0+ 1, AB1+ 1 . . . ABx 1+ 1 and nBx+ 1 signal pulses applied at the signal input of the first stage of said gate control apparatus, where x is an integer representing the number of stages in said gate control apparatus and n is an integer zero (0) or greater; a source of reference frequency signal pulses; decade counting and display means having an input and having an output responsive to the number of cycles a signal has been applied to said input for displaying said number in digitized form; switching means having an output connected to the input of said decade counting and display means and having a first input connected to receive an input signal to be counted, a second input and a third input connected to the gated output of the last stage of said gate control apparatus for connecting the input signal to be counted at said first input to the output of said switching means in response to a signal appearing at said third input of said switching means and for disconnecting said input signal to be counted from the output of said switching means in response to the first signal that appears at said third input after a signal has appeared at said second input; and means having an input connected to the output of said decade counting and display means and having an output connected to the second input of said signal switching means for producing a signal in response to a certain number being registered in said decade counting and display means.
Claim 3
Dependent Claim 33 words
Apparatus as in claim 1 and including means connecting the carry output from a stage of said gate control apparatus to the second input of said switching means for providing a signal thereto.
Claim 4
Dependent Claim 47 words
Apparatus as in claim 2 comprising decimal point positioning means having an input connected to the gated output of the third gating means of said last stage and having an output responsive to the number of signal pulses appearing at said input for displaying a decimal point.

References Cited (Backward Citations)

US3062443A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-04-23 1976-10-23 1977-04-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-04-23 1980-10-23 1981-04-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-04-23 1984-10-23 1985-04-24 $7700.00 Window Closed / Lapsed

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