Electronic timepiece with frequency correction

Claim 2

A time correction circuit for an electronic timepiece comprising: an oscillator circuit outputting a high frequency standard signal; a divider network having a plurality of divider stages in a chain of division, said divider network dividing down said high frequency standard signal, at least one of said divider stages having at least one of a setting and resetting input terminal; means for timekeeping driven by the divided down output of said divider network; means for imposing, when driven, a selected output condition on said at least one of said plurality of divider stages, said at least one divider stage being adapted for one of setting, resetting, and setting and resetting by a signal from said means for imposing, said signal being applied to said input terminal of said at least one divider stage outside of said chain of division; at least one correction data terminal connected to said means for imposing, said at least one data terminal having a preselected logic condition thereon at the moment when said at least one divider stage is driven for one of setting and resetting for imposing a selected output signal, said pre-selected logic condition of said at least one data terminal determining said selected output condition on said at least one divider stage by said setting and resetting; control means for driving, when actuated, said means for imposing a selected output condition; detection means for sensing a first preferred output condition of one of said divider stages, said one stage being an intermediate stage of said divider network, said detection means, having sensed said first preferred output, being adapted to actuate said control means, said detection means for sensing being enabled by a second preferred output condition, from one of said plurality of divider stages, said second preferred output condition occurring periodically at a stage in said divider network after said first preferred output condition, occurrence of said first preferred output following said second preferred output causing a selected output on said at least one divider stage by said setting and resetting and the timing rate of said divider network is modified thereby.

Claim 3

The time correction circuit as claimed in claim 1, wherein said detection means is a set-reset circuit adapted to respond alternately to said first and second preferred output conditions.

Claim 4

The time correction circuit as claimed in claim 1, wherein said selected output is imposed by setting said at least one divider stage.

Claim 5

The time correction circuit as claimed in claim 1, wherein said selected output is imposed by resetting said at least one divider stage.

Claim 6

The time correction circuit as claimed in claim 1, wherein selected outputs are imposed on at least two divider stages, one of said at least two divider stages being reset, and another of said at least two divider stages being set by said imposition.

Claim 7

A time correction circuit for an electronic timepiece comprising: an oscillator circuit outputting a high frequency standard signal; a divider network having a plurality of divider stages in a chain of division, said divider network dividing down said high frequency standard signals, at least one of said divider stages having at least one of a setting and resetting input terminal; means for timekeeping driven by the divided down output of said divider network; means for imposing, when driven, a selected output condition on said at least one of said plurality of divider stages said at least one divider stage being adapted for one of setting, resetting and setting and resetting by a signal from said means for imposing, said signal being applied to said input terminal of said at least one divider stage outside of said chain of division; at least one correction data terminal connected to said means for imposing, said at least one data terminal having a preseleted logic condition thereon at the moment when said at least one divider stage is driven for said setting and resetting for imposing a selected output signal, said pre-selected logic condition of said at least one data terminal determining said selected output condition on said at least one divider stage by said setting and resetting; control means for driving, when actuated, said means for imposing a selected output condition; detection means for sensing a first and a second preferred output condition of two of said divider stages, said two divider stages being intermediate stages of said divider network, said detection means having sensed said first and said second preferred output conditions, being adapted to actuate said control means, said detection means for sensing being enabled by a third and fourth preferred output condition, said third and fourth preferred output conditions occurring at stages in said divider network after said first and second preferred conditions, occurrence of said first and second preferred output conditions following said third and fourth preferred output conditions causing a selected output on said at least one divider stage by said setting and resetting and the timing rate of said divider network is modified thereby.

Claim 8

A time correction circuit for an electronic timepiece comprising: an oscillator circuit outputting a high frequency standard signal; a divider network having a plurality of divider stages in a chain of division, said divider network dividing down said high frequency standard signals, at least one of said divider stages having at least one of a setting and resetting input terminal; means for timekeeping driven by the divided down output of said divider network; means for imposing, when driven, a selected output condition on said at least one of said plurality of divider stages said at least one divider stage being adapted for one of setting, resetting and setting and resetting by a signal from said means for imposing, said signal being applied to said input terminal of said at least one divider stage outside of said chain of division; at least one correction data terminal connected to said means for imposing, said at least one data terminal having a preseleted logic condition thereon at the moment when said at least one divider stage is driven for said setting and resetting for imposing a selected output signal, said pre-selected logic condition of said at least one data terminal determining said selected output condition on said at least one divider stage by said setting and resetting; control means for driving, when actuated, said means for imposing a selected output condition; detection means for sensing a first and a second preferred output condition of two of said divider stages, said two divider stages being intermediate stages of said divider network, said detection means having sensed said first and said second preferred output conditions, being adapted to actuate said control means, said detection means for sensing being enabled by a third and fourth preferred output condition, said third and fourth preferred output conditions occurring at stages in said divider network after said first and second preferred conditions, occurrence of said first and second preferred output conditions following said third and fourth preferred output conditions causing a selected output on said at least one divider stage by said setting and resetting and the timing rate of said divider network is modified thereby.

Claim 9

The time correction circuit as claimed in claim 6, wherein said third and fourth preferred output conditions are selected from different ones of said plurality of divider stages.

Claim 10

The time correction circuit as claimed in claim 7, wherein said third preferred output condition enables said detection means for sensing said first preferred output condition, and said fourth preferred output condition enables said detection means for sensing said second preferred output condition, whereby selected outputs are imposed at different repetition rates.

Claim 11

The time correction circuit as claimed in claim 8, wherein said detection means includes a pair of set-reset circuits, one said set-reset circuit being adapted to respond alternately to said first and third preferred output conditions and the other set-reset circuit being adapted to respond alternately to said second and fourth preferred output conditions.

Claim 12

The time correction circuit as claimed in claim 9, wherein selected outputs are imposed on at least two divider stages, one of said at least two divider stages being reset, and another of said at least two divider stages being set by said imposition.

Claim 13

The time correction circuit as claimed in claim 9, wherein there is a plurality of said data terminals, one portion of said data terminals cooperating with one said set-reset circuit, another portion of said data terminals cooperating with the other said set-reset circuit, whereby coarse and fine adjustments can be made.

Claim 14

The time correction circuit as claimed in claim 1 or 9, wherein the first preferred output condition is detected on the divider stage on which a selected output condition is imposed.

Claim 15

The time correction circuit as claimed in claim 1 or 9, wherein the first preferred output condition is detected on another divider stage from the divider stage on which a selected output is imposed.

Claim 16

The time correction circuit as claimed in claim 9, wherein the second preferred output condition is detected on a divider stage on which a selected output condition is imposed.

Claim 17

The time correction circuit as claimed in claim 9, wherein the second preferred output condition is detected on another divider stage from the divider stage on which a selected output is imposed.