US3895486A
Expired / Lapsed
US
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Timekeeper
Assignee: Centre Electronique Horloger SA
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Filing: 1972-03-21
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Granted: 1975-07-22
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Expires: 1992-03-21
Abstract
Abstract A timekeeper comprises a quartz crystal resonator having a stable frequency but with a relatively large tolerance, and a frequency divider with an adjustable divison ratio. Said divider has auxiliary electrical inputs the logical state of which determines the division ratio, and a memory, for example an electrically alterable electronic memory, supplies stored data to determine the logical state of the auxiliary inputs and hence the division ratio. The memory may comprise volatile and permanent parts, the permanent part intermittently regenerating data stored in the volatile part.
Inventors
- 👤 Walter Hammer
- 👤 Eric Andre Vittoz
- 👤 Jean Hermann
- 👤 Hubert Choffat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:12
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/662; G; G04; G04G; G04G3/00; G04G3/02; G04G3/022; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
213 words
A self-adjusting timekeeping apparatus comprising: a resonator producing a pulsed output signal having a non-adjusted frequency; a frequency divider coupled to said resonator for dividing the frequency of the output singal of said resonator, said frequency divider including auxiliary input means for adjusting the frequency division ratio thereof; memory means for storing coded data in the form of a plurality of binary data bits; and frequency adjusting means coupling said memory means to said auxiliary input means for adjusting the frequency division ratio of said frequency divider as a function of the coded data stored in said memory means to thereby adjust the output frequency of said frequency divider, said frequency adjusting means including means for comparing the binary coded data bits stored in said memory means with a corresponding plurality of data bits produced at intermediate outputs of said divider, means coupled to said comparing means for generating an output signal when at least one set of compared memory and divider data bits are in coincidence, said output signal comprising a plurality of pulses the number of which is determined by said binary coded data bits stored in said memory means, and means for feeding said output signal back to said auxiliary input means for adjusting the output frequency of said divider.
Claim 2
Dependent Claim
213 words
A self-adjusting timekeeping apparatus comprising: a resonator producing a pulsed output signal having a non-adjusted frequency; a frequency divider coupled to said resonator for dividing the frequency of the output singal of said resonator, said frequency divider including auxiliary input means for adjusting the frequency division ratio thereof; memory means for storing coded data in the form of a plurality of binary data bits; and frequency adjusting means coupling said memory means to said auxiliary input means for adjusting the frequency division ratio of said frequency divider as a function of the coded data stored in said memory means to thereby adjust the output frequency of said frequency divider, said frequency adjusting means including means for comparing the binary coded data bits stored in said memory means with a corresponding plurality of data bits produced at intermediate outputs of said divider, means coupled to said comparing means for generating an output signal when at least one set of compared memory and divider data bits are in coincidence, said output signal comprising a plurality of pulses the number of which is determined by said binary coded data bits stored in said memory means, and means for feeding said output signal back to said auxiliary input means for adjusting the output frequency of said divider.
Claim 3
Dependent Claim
82 words
The apparatus according to claim 1, wherein said comparing means comprises: a plurality of EXCLUSIVE OR gates having first inputs coupled to corresponding outputs of said memory means and second inputs coupled to corresponding ones of said intermediate frequency divider outputs; and said output signal generating means comprises an AND gate having a plurality of inputs coupled to respective outputs of said EXCLUSIVE OR gates, the output of said AND gate being coupled to said auxiliary input means by said feedback means.
Claim 4
Dependent Claim
32 words
The apparatus according to claim 2, wherein said auxiliary input means includes means to reset said frequency divider to zero as a function of an output signal produced by said AND gate.
Claim 5
Dependent Claim
124 words
The apparatus according to claim 1, wherein: said auxiliary input means comprises a NAND gate having a first input coupled to the output of said resonator and an output coupled to an input of said frequency divider; and said comparing means comprises a plurality of AND gates having first inputs coupled to corresponding outputs of said memory means and second inputs coupled to corresponding ones of said frequency divider intermediate outputs. said output signal generating means comprising and OR gate having a plurality of inputs coupled to respective outputs of said AND gates, and said feedback means comprises an RS flip-flop having an input coupled to an output of said OR gate and an output coupled to a second input of said NAND gate.
Claim 6
Dependent Claim
30 words
The apparatus according to claim 4, further comprising means for inverting an output signal of said resonator interposed between said resonator output and a second input of said RS flip-flop.
Claim 7
Dependent Claim
44 words
The apparatus according to claim 1, wherein said auxiliary inpt means comprises means coupled to said output signal generating means for inhibiting only a single pulse of the divided resonator output signal during the period of each pulse of said generating means output signal.
Claim 8
Dependent Claim
118 words
The apparatus according to claim 1, wherein: said frequency divider comprises a chain of dividing stages; said auxiliary input means comprises intermediary circuit means coupled in series in said divider chain for supplying to succeeding divider stages in said chain a mean number of pulses different from the mean number of pulses received at its input, the difference between said mean numbers of pulses corresponding to a number stored in said memory; and said feedback, means comprises a control circuit having one input coupled to at least one output of one stage of said dividing chain, a second input coupled to said output signal generating means, and an output coupled to an input of said intermediary circuit means.
Claim 9
Dependent Claim
21 words
The apparatus according to claim 7, further comprising a time display member coupled to an intermediate output of said dividing chain.
Claim 10
Dependent Claim
51 words
The apparatus according to claim 7, in which the frequency of the resonator is greater than a nominal frequency corresponding to the minimum division ratio of the divider, said intermediary circuit being a transmission stage comprising means for making a single division by two when a control pulse is applied thereto.
Claim 11
Dependent Claim
15 words
The apparatus according to claim 7, in which the intermediary circuit is a pulse adder.
Claim 12
Dependent Claim
140 words
The apparatus according to claim 1, wherein said comparing means comprises first gate means for gating the intermediate outputs of said divider with the stored data outputs from said memory means and said signal generating means comprises means for generating a first logic signal having a duration which is determined by the coded data stored in said memory means; suppressor means coupled to the output of said signal generating means for suppressing all outputs from said first gate means other than said first logic signal during a preset period; and said feedback means comprising further gate means for gating the output of said suppressor means with a further intermediate output of said frequency divider, the output of said further gate means being fed back to the auxiliary input means of said frequency divider to adjust the frequency division ratio thereof.
Claim 13
Dependent Claim
31 words
The apparatus according to claim 11, wherein the output Of the last stage of said frequency divider is coupled to said suppressor means to determine the length of said preset period.
Claim 14
Dependent Claim
25 words
Timekeeper according to claim 1, in which the memory is an electrically alterable memory having at least one electrical input for the inscription of data.
Claim 15
Dependent Claim
14 words
Timekeeper according to claim 13, in which the memory is a volatile electronic memory.
Claim 16
Dependent Claim
17 words
Timekeeper according to claim 13, in which the memory is a memory with sequential inscription of data.
Claim 17
Dependent Claim
13 words
Timekeeper according to claim 15, in which the memory is a shift register.
Claim 18
Dependent Claim
13 words
Timekeeper according to claim 13, in which the memory is a permanent memory.
Claim 19
Dependent Claim
18 words
Timekeeper according to claim 13, in which the memory comprises a volatile memory coupled with a permanent memory.
Claim 20
Dependent Claim
31 words
Timekeeper according to claim 13, in which the memory comprises a permanent memory for large corrections to the division ratio and a volatile memory for small corrections to the division ratio.
Claim 21
Dependent Claim
25 words
Timekeeper according to claim 13, in which the memory comprises at least one inscription input connected to a logical variable which controls time display means.
Claim 22
Dependent Claim
18 words
Timekeeper according to claim 2, comprising autonomous means coupled to and supplying the memory with frequency adjustment signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-21 | 1979-01-20 | 1979-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-21 | 1983-01-20 | 1983-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-21 | 1987-01-20 | 1987-07-22 | $7700.00 | Window Closed / Lapsed |