US4374332A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cascade type CMOS semiconductor device
Assignee: Seiko Instruments Inc
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Filing: 1980-09-16
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Granted: 1983-02-15
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Expires: 2000-09-16
Abstract
Abstract Within a semiconductor device having two sets of CMOS inverters, the two sets of CMOS inverters are electrically connected in series to a power source for supplying electric power to the semiconductor device. The two sets of CMOS inverters are formed in an oscillating circuit for producing a time base signal and a frequency dividing circuit, respectively. Device operating current and power consumption are accordingly reduced.
Inventors
- 👤 Nobuo Inami
- 👤 Kojiro Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:31
CPC Classifications
G; G04; G04G; G04G19/00; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0307
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
269 words
A CMOS semiconductor device, comprising: a first CMOS circuit having input, output and power terminals and comprising a CMOS transistor pair having the source of one transistor and the drain of the other transistor connected together at a node to define said output terminal and for connecting the respective transistor channels in series, having the respective gates of said transistors connected together to define said input terminal, and wherein the drain of said one transistor and the source of said other transistor define said power terminals; a second CMOS circuit having input, output and power terminals and comprising a CMOS transistor pair having the source of one transistor and the drain of the other transistor connected together at a node to define said output terminal and for connecting the respective transistor channels in series, having the respective gates of said transistors connected together to define said input terminal, and wherein the drain of said one transistor and the source of said other transistor define said power terminals; respective power terminals of said first and second CMOS circuits being connected together so that the channels of their respective CMOS transistor pairs are connected in series; a signal lead free of reactive circuit elements and connecting said output terminal of said CMOS transistor pair of said first CMOS circuit to said input terminal of said CMOS transistor pair of said second CMOS circuit; and wherein said transistors comprising said CMOS transistor pairs have respective threshold voltage values effective to allow signal transmission from said output terminal to said input terminal substantially without current flow between said first and second CMOS circuits.
Claim 2
Dependent Claim
269 words
A CMOS semiconductor device, comprising: a first CMOS circuit having input, output and power terminals and comprising a CMOS transistor pair having the source of one transistor and the drain of the other transistor connected together at a node to define said output terminal and for connecting the respective transistor channels in series, having the respective gates of said transistors connected together to define said input terminal, and wherein the drain of said one transistor and the source of said other transistor define said power terminals; a second CMOS circuit having input, output and power terminals and comprising a CMOS transistor pair having the source of one transistor and the drain of the other transistor connected together at a node to define said output terminal and for connecting the respective transistor channels in series, having the respective gates of said transistors connected together to define said input terminal, and wherein the drain of said one transistor and the source of said other transistor define said power terminals; respective power terminals of said first and second CMOS circuits being connected together so that the channels of their respective CMOS transistor pairs are connected in series; a signal lead free of reactive circuit elements and connecting said output terminal of said CMOS transistor pair of said first CMOS circuit to said input terminal of said CMOS transistor pair of said second CMOS circuit; and wherein said transistors comprising said CMOS transistor pairs have respective threshold voltage values effective to allow signal transmission from said output terminal to said input terminal substantially without current flow between said first and second CMOS circuits.
Claim 3
Dependent Claim
74 words
A CMOS semiconductor device according to claim 1: wherein said first CMOS circuit is an oscillator circuit for generating an oscillating time base signal; and wherein said second CMOS circuit is comprised of a frequency divider circuit and a buffer circuit having an input terminal connected to said signal lead for receiving and shaping the oscillating time base signal from said oscillator circuit and for applying the shaped signal to said frequency divider circuit.
Claim 4
Dependent Claim
31 words
A CMOS semiconductor device according to claim 1 or 2, further comprising: a power source, and wherein said first and second CMOS circuits are connected in series with said power source.
Claim 5
Dependent Claim
41 words
A CMOS semiconductor device according to claim 1 or 2, wherein: said first and second CMOS circuits together comprise an integrated circuit; and wherein said integrated circuit comprises means for electrically isolating said first CMOS circuit from said second CMOS circuit.
Claim 6
Dependent Claim
144 words
A CMOS semiconductor device according to claim 1 or 2: wherein said first CMOS circuit is comprised of first and second CMOS transistors having their respective channels connected in series; wherein said second CMOS circuit is comprised of third and fourth CMOS transistors having their respective channels connected in series, fifth and sixth CMOS transistors having their respective channels connected in series, and the pair of third and fourth transistors are connected with the series connection of their respective channels in parallel with the series connection of the respective channels of said fifth and sixth CMOS transistors; wherein said first transistor is connected to said fourth and sixth transistors; and wherein said transistors have the following respective approximate threshold voltages; first transistor: -0.3 V, second transistor: +0.3 V, third transistor: -1.1 V, fourth transistor: -0.5 V, fifth transistor: -0.3 V, sixth transistor: +0.3 V.
Claim 7
Dependent Claim
15 words
A CMOS semiconductor device according to claim 5, further comprising a 1.5 volt power source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-14 | 1986-08-16 | 1987-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-14 | 1990-08-16 | 1991-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-14 | 1994-08-16 | 1995-02-15 | $7700.00 | Window Closed / Lapsed |