Random access memory with volatile and non-volatile storage

Claim 2

The combination comprising: a volatile binary storage element having first and second power terminals for the application of an operating potential therebetween and having first and second input output (I/O) points; a bit line, and a word line; a gating transistor having a conduction path and a control electrode; means connecting said conduction path of said gating transistor between one of said I/O points and said bit line; and means connecting said control electrode to said word line; a non-volatile storage element which can be programmed to either one of two conductive states; and a switch means, coupled to said non-volatile storage element, responsive to a given potential difference applied between said word line and one of said first and second power terminals for selectively connecting said non-volatile storage element in circuit with said volatile binary storage element between said word line and one of said first and second input-output points.

Claim 3

The combination as claimed in claim 1 wherein said switch means includes a switching transistor having first and second electrodes defining the ends of its conduction path and a control electrode, means connecting said conduction path of said switching transistor between said word line and said non-volatile storage element, and means connecting said control electrode of said switching transistor to said one of said first and second power terminals.

Claim 4

The combination as claimed in claim 2 wherein said non-volatile storage element is a normally non-conducting floating gate insulated-gate field-effect transistor having a conduction path and said non-volatile element assuming a conduction state in response to the application of a voltage greater than a given voltage V R across its conduction path.

Claim 5

The combination as claimed in claim 3 wherein said volatile storage element includes first and second inverters, each inverter having an input, an output and first and second operating voltage terminals, wherein the output of the first inverter is connected to the input of the second inverter at said first input-output point and the output of the second inverter is connected to the input of the first inverter at said second input-output point; wherein the first operating voltage terminals of said first and second inverters are connected to said first power terminal; and wherein said second operating voltage terminals of said first and second inverters are connected to said second power terminal.

Claim 6

The combination as claimed in claim 2 further including means for selectively applying potentials to said word line and said power terminals for turning-on said gating transistors while concurrently turning off said switching transistor, and for selectively turning on said switching transistor while concurrently turning off said gating transistor.

Claim 7

The combination as claimed in claim 1 including means for: (a) applying a given operating potential across said first and second power terminals of said volatile storage element when information is being written into said volatile section from said bit line or read out from said volatile section onto said bit line; (b) increasing said operating potential across said volatile storage element when information is being transferred from said volatile section to said non-volatile section; and (c) decreasing the operating potential across said volatile storage element when information is being transferred from said non-volatile section to said volatile section.

Claim 8

The combination comprising: a volatile binary storage element having first and second power terminals for the application of an operating potential therebetween and having first and second input output (I/O) points; a bit line; means coupled between said bit line and one of said I/O points for selectively writing the information on said bit line into said volatile storage element or selectively reading out the information in said volatile storage element onto said bit line; a non-volatile storage element which can be programmed to eiter one of two conductive states; and means coupling said non-volatile storage element to one of said I/O points of said volatile storage elements for selectively transferring information from said non-volatile to said volatile section, said means including means for: (a) applying a given operating potential across said first and second power terminals of said volatile storage element when information is being written into said volatile section from said bit line or read out from said volatile section onto said bit line; (b) increasing said given operating potential across said volatile storage element when information is being transferred from said volatile section to said non-volatile section; and (c) decreasing said given operating potential across said volatile storage element relative to the non-volatile storage element when information is being transferred from said non-volatile section to said volatile section.

Claim 9

The combination comprising: a volatile binary storage element having first and second power terminals for the application of an operating potential therebetween and having first and second input output (I/O) points; a bit line; means coupled between said bit line and one of said I/O points for selectively writing the information on said bit line into said volatile storage element or selectively reading out the information in said volatile storage element onto said bit line; a non-volatile storage element which can be programmed to eiter one of two conductive states; and means coupling said non-volatile storage element to one of said I/O points of said volatile storage elements for selectively transferring information from said non-volatile to said volatile section, said means including means for: (a) applying a given operating potential across said first and second power terminals of said volatile storage element when information is being written into said volatile section from said bit line or read out from said volatile section onto said bit line; (b) increasing said given operating potential across said volatile storage element when information is being transferred from said volatile section to said non-volatile section; and (c) decreasing said given operating potential across said volatile storage element relative to the non-volatile storage element when information is being transferred from said non-volatile section to said volatile section.