Patent US4346452A successfully refreshed from Google Patents.
US4346452A
Expired / Lapsed
US
⏱️ 0.0 years remaining
NRZ/Biphase microcomputer serial communication logic
Assignee: Motorola Solutions Inc
•
Filing: 1978-09-05
•
Granted: 1982-08-24
•
Expires: 1998-09-05
Abstract
Abstract A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic is capable of handling serial communications in either the NRZ or Manchester (biphase) format. The result is more versatile and more reliable serial communications.
Inventors
- 👤 Stanley E. Groves
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:47
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
143 words
In a microcomputer including a processor, serial I/O communication logic and bus means for coupling said processor to said serial I/O communication logic, said serial I/O communication logic comprising: control register means coupled to said processor, for storing transmit mode and receive mode signals provided by said processor, transmitter means coupled to said processor, for receiving and storing data provided periodically by said processor, and for serially transmitting said stored data via a serial output line in either NRZ or biphase format as selected by said transmit mode signal stored in said control register means, and receiver means coupled to said processor, for serially receiving data via a serial input line in either NRZ or biphase format as selected by said receive mode signal stored in said control register means, storing said received data, and periodically providing said stored data to said processor.
Claim 2
Dependent Claim
143 words
In a microcomputer including a processor, serial I/O communication logic and bus means for coupling said processor to said serial I/O communication logic, said serial I/O communication logic comprising: control register means coupled to said processor, for storing transmit mode and receive mode signals provided by said processor, transmitter means coupled to said processor, for receiving and storing data provided periodically by said processor, and for serially transmitting said stored data via a serial output line in either NRZ or biphase format as selected by said transmit mode signal stored in said control register means, and receiver means coupled to said processor, for serially receiving data via a serial input line in either NRZ or biphase format as selected by said receive mode signal stored in said control register means, storing said received data, and periodically providing said stored data to said processor.
Claim 3
Dependent Claim
63 words
The microcomputer recited in claim 1, wherein said control register also stores transmit enable and receive enable signals provided by said processor, wherein said transmitter means are operative only in response to said transmit enable signal stored in said control register means, and wherein said receiver means are operative only in response to said receive enable signal stored in said control register means.
Claim 4
Dependent Claim
63 words
The microcomputer recited in claim 1, wherein said control register also stores transmission rate and reception rate signals provided by said processor, wherein said transmitter means transmit at a rate selected by said transmission rate signal stored in said control register means, and wherein said receiver means receive at a rate selected by said reception rate signal stored in said control register means.
Claim 5
Dependent Claim
107 words
The microcomputer recited in claim 1, wherein said serial I/O communication logic operates in synchronization with a clock signal, wherein said microcomputer further comprises an internal clock source for generating an internal clock signal and a terminal for receiving an external clock signal from an external clock source, and wherein said control register also stores a clock source signal provided by said processor, said serial I/O communication logic further comprising: means coupled to said control register for operating said serial I/O communication logic in synchronization with said internal clock signal or said external clock signal as selected by said clock source signal stored in said control register.
References Cited (Backward Citations)
US4066964A
Cited
US3618031A
Cited
US3760277A
Cited
US3988676A
Cited
US3863025A
Cited
US4087855A
Cited
US3987374A
Cited
US4006416A
Cited
US3975712A
Cited
US3983485A
Cited
US4016548A
Cited
US4038494A
Cited
US4071887A
Cited
US4047201A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-23 | 1986-02-22 | 1986-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-23 | 1990-02-22 | 1990-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-23 | 1994-02-22 | 1994-08-24 | $7700.00 | Window Closed / Lapsed |