US4047201A — I/O Bus transceiver for a data processing system

Claim 1

Independent Claim 344 words

In a data processing system including (a) CPU, (b) a main memory interfacing with said CPU, (c) I/O means, incuding a plurality of device controllers, for connecting between said CPU and a like plurality of peripheral devices, and (d) a clock source, transceiver means contained within said I/O means for serially transmitting and receiving unmodulated signals between said CPU and said plurality of device controllers, said transceiver means comprising: a CPU transceiver; a first group of conductors for connecting said CPU transceiver from said CPU: a like plurality of device control transceivers; a like plurality of second groups of conductors each of said second groups for connecting each of said device control transceivers to each of said device controllers respectively; an I/O bus connected at least between said CPU transceiver and said device control transceivers, said I/O bus including multiple data signal paths, clock signal paths, and control signal paths; said CPU transceiver including means for (1) receiving pulses from said clock source, (2) employing said pulses as a local clock, (3) transmitting said pulses to one of said clock signal paths of said I/O bus, and (4) conducting said pulses to certain of said first group of conductors; each of said device control transceivers including means for (1) receiving said transmitted pulses from said one of said clock signal paths, (2) employing said transmitted pulses as its respective local clock, and (3) conducting said transmitted pulses to certain conductors of a respective one of said second groups of conductors; said CPU transceiver including mode control means normally operative to maintain said CPU transceiver in a receiving mode and responsive to a mode control signal on one of said conductors of said first group for establishing a transmit mode for said CPU transceiver; and, each of said device control transceivers including other mode control means normally operative to maintain said device control transceivers in a receiving mode and responsive to other mode control signals from respective ones of said device controllers for establishing a transmit mode for respective ones of said device control transceivers.

Claim 2

Dependent Claim 344 words

In a data processing system including (a) CPU, (b) a main memory interfacing with said CPU, (c) I/O means, incuding a plurality of device controllers, for connecting between said CPU and a like plurality of peripheral devices, and (d) a clock source, transceiver means contained within said I/O means for serially transmitting and receiving unmodulated signals between said CPU and said plurality of device controllers, said transceiver means comprising: a CPU transceiver; a first group of conductors for connecting said CPU transceiver from said CPU: a like plurality of device control transceivers; a like plurality of second groups of conductors each of said second groups for connecting each of said device control transceivers to each of said device controllers respectively; an I/O bus connected at least between said CPU transceiver and said device control transceivers, said I/O bus including multiple data signal paths, clock signal paths, and control signal paths; said CPU transceiver including means for (1) receiving pulses from said clock source, (2) employing said pulses as a local clock, (3) transmitting said pulses to one of said clock signal paths of said I/O bus, and (4) conducting said pulses to certain of said first group of conductors; each of said device control transceivers including means for (1) receiving said transmitted pulses from said one of said clock signal paths, (2) employing said transmitted pulses as its respective local clock, and (3) conducting said transmitted pulses to certain conductors of a respective one of said second groups of conductors; said CPU transceiver including mode control means normally operative to maintain said CPU transceiver in a receiving mode and responsive to a mode control signal on one of said conductors of said first group for establishing a transmit mode for said CPU transceiver; and, each of said device control transceivers including other mode control means normally operative to maintain said device control transceivers in a receiving mode and responsive to other mode control signals from respective ones of said device controllers for establishing a transmit mode for respective ones of said device control transceivers.

Claim 3

Dependent Claim 160 words

In a data processing system for processing data including a CPU and peripheral device controllers, transceiver means for transmitting and receiving signals between said CPU and said controllers comprising: a CPU transceiver; respective controller transceivers; bus means for connecting said CPU transceiver and said controller transceivers; said CPU transceiver and said controller transceivers each including mode control means normally operative for maintaining each respective transceiver in an input mode; said mode control means including other means responsive to one signal from said CPU and said controllers for establishing an output mode for one of said CPU transceiver and said controller transceivers respectively; and said one of said CPU transceiver and said controller transceivers responsive to operation of said other means for receiving an I/O clock burst and a word of said data synchronized and corresponding therewith from one of said CPU and said controllers and for transmitting synchronously a BIO clock burst and said data word over said bus means.

Claim 4

Dependent Claim 160 words

In a data processing system for processing data including a CPU and peripheral device controllers, transceiver means for transmitting and receiving signals between said CPU and said controllers comprising: a CPU transceiver; respective controller transceivers; bus means for connecting said CPU transceiver and said controller transceivers; said CPU transceiver and said controller transceivers each including mode control means normally operative for maintaining each respective transceiver in an input mode; said mode control means including other means responsive to one signal from said CPU and said controllers for establishing an output mode for one of said CPU transceiver and said controller transceivers respectively; and said one of said CPU transceiver and said controller transceivers responsive to operation of said other means for receiving an I/O clock burst and a word of said data synchronized and corresponding therewith from one of said CPU and said controllers and for transmitting synchronously a BIO clock burst and said data word over said bus means.

Claim 5

Dependent Claim 86 words

The data processing system of claim 2 and wherein said BIO clock burst is about double the frequency of said data word, said data word comprising a train of pulses, said CPU transceiver and said controller transceivers each including: sampling means responsive to receipt of said BIO clock burst and said data word from said bus means for sampling said pulses when edges of said BIO clock burst occur near centers of said pulses, whereby each pulse of said data word is sampled at an-away-from-data-edge position.

Claim 6

Dependent Claim 222 words

In a data processing system including a CPU and at least one peripheral device controller, transceiver means including a CPU transceiver and at least one peripheral device controller transceiver for transmitting and receiving signals between said CPU and said peripheral device controller, said transceiver means comprising: means for developing local clock pulses of predetermined frequency in said CPU transceiver and said peripheral device controller transceiver, the local clock pulses of said peripheral device controller transceiver being phase shifted from the local clock pulses of said CPU transceiver as a function of conductive distance therebetween; first deriving means responsive to said developing means for deriving CPU clock pulses of less than said predetermined frequency from said local clock pulses of said CPU transceiver and for conducting said CPU clock pulses to said CPU; second deriving means responsive to said developing means for deriving peripheral device controller clock pulses of said less than said predetermined frequency from said local clock pulses of said peripheral device controller transceiver and for conducting said peripheral device controller clock pulses to said peripheral device controller; and first means for receiving said signals from said CPU synchronized by a burst of said CPU clock pulses and for transmitting said signals synchronously with a burst of said local clock pulses of said CPU transceiver to said peripheral device controller transceiver.

Claim 7

Dependent Claim 222 words

In a data processing system including a CPU and at least one peripheral device controller, transceiver means including a CPU transceiver and at least one peripheral device controller transceiver for transmitting and receiving signals between said CPU and said peripheral device controller, said transceiver means comprising: means for developing local clock pulses of predetermined frequency in said CPU transceiver and said peripheral device controller transceiver, the local clock pulses of said peripheral device controller transceiver being phase shifted from the local clock pulses of said CPU transceiver as a function of conductive distance therebetween; first deriving means responsive to said developing means for deriving CPU clock pulses of less than said predetermined frequency from said local clock pulses of said CPU transceiver and for conducting said CPU clock pulses to said CPU; second deriving means responsive to said developing means for deriving peripheral device controller clock pulses of said less than said predetermined frequency from said local clock pulses of said peripheral device controller transceiver and for conducting said peripheral device controller clock pulses to said peripheral device controller; and first means for receiving said signals from said CPU synchronized by a burst of said CPU clock pulses and for transmitting said signals synchronously with a burst of said local clock pulses of said CPU transceiver to said peripheral device controller transceiver.

Claim 8

Dependent Claim 62 words

In the system of claim 4, second means, operative mutually exclusively with the operation of said first means, for receiving said signals from said peripheral device controller synchronized by a burst of said peripheral device controller clock pulses and for transmitting said signals synchronously with a burst of said local clock pulses of said peripheral device controller transceiver to said CPU transceiver.

Claim 9

Dependent Claim 49 words

In the system of claim 5, said CPU transceiver including fourth means responsive to receipt of said peripheral device controller transceiver local clock pulse burst for sampling said signals when certain edges of said peripheral device controller transceiver local clock pulse burst occur away from edges of said signals.

Claim 10

Dependent Claim 12 words

The system of claim 6, and wherein said signals are information pulses.

Claim 11

Dependent Claim 47 words

In the system of claim 4, said peripheral device controller transceiver including third means responsive to receipt of said CPU transceiver local clock pulse burst for sampling said signals when certain edges of said CPU transceiver local clock pulse burst occur away from edges of said signals.

Claim 12

Dependent Claim 12 words

The system of claim 8, and wherein said signals are information pulses.

Claim 13

Dependent Claim 24 words

In the system of claim 4, said transceiver means further including bus means for conductively connecting said CPU transceiver and said peripheral device transceiver.

Claim 14

Dependent Claim 19 words

The system of claim 4 and wherein said less than said predetermined frequency is approximately half said predetermined frequency.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1980-09-05	1981-03-07	1981-09-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1984-09-05	1985-03-07	1985-09-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1988-09-05	1989-03-07	1989-09-06	$7700.00	Window Closed / Lapsed

I/O Bus transceiver for a data processing system

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