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US4323910A Expired / Lapsed US ⏱️ 0.0 years remaining

MNOS Memory transistor

Assignee: RCA Corp
•
Filing: 1977-11-28
•
Granted: 1982-04-06
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Expires: 1997-11-28
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Abstract

Abstract A memory transistor includes a body of semiconductor material having therein a channel region of one conductivity type and source and drain regions of the opposite conductivity type. A channel insulation is on the surface of the semiconductor body and extends over the channel region. The channel insulation includes a first layer of silicon dioxide directly on the surface of the semiconductor body and a layer of silicon nitride on the silicon dioxide layer. A gate of conductive polycrystalline silicon is preferable provided on the channel insulation. The channel of the transistor is sufficiently narrow so that electrons can be avalanched into the interface between the silicon nitride layer and the silicon dioxide layer completely across the full width of the channel where the electrons can be stored.

Inventors

  • 👤 Joseph C. Sokoloski
  • 👤 Alfred C. Ipri

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 06:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6758; H10D30/6759; H10D30/6729; H10D30/6737; H10D30/6739; H10D30/69

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 97 words
A MNOS memory transistor comprising: a body of semiconductor material having along a surface thereof a source region, a drain region, and a channel region between said source and drain regions, a channel insulation on said surface of the semiconductor body and over said channel region, said channel insulation including two layers of different material which are capable of storing at the interface electrons which are injected into the channel insulation, and said channel being sufficiently narrow in width that the electrons will be injected into the channel insulation completely across the channel region by avalanche injection.
Claim 2
Dependent Claim 97 words
A MNOS memory transistor comprising: a body of semiconductor material having along a surface thereof a source region, a drain region, and a channel region between said source and drain regions, a channel insulation on said surface of the semiconductor body and over said channel region, said channel insulation including two layers of different material which are capable of storing at the interface electrons which are injected into the channel insulation, and said channel being sufficiently narrow in width that the electrons will be injected into the channel insulation completely across the channel region by avalanche injection.
Claim 3
Dependent Claim 53 words
A MNOS memory transistor in accordance with claim 1 in which the width of the channel is no greater than Lc≦(εΣ/eC.sub.B) where Lc=channel width, ε=the dielectric constant of the semiconductor material, Σ=the critical field value for the semiconductor material, e=the charge on an electron, C B =the doping concentration in the semiconductor body.
Claim 4
Dependent Claim 26 words
A MNOS memory transistor in accordance with claim 2 in which the channel insulation includes a layer of silicon dioxide and a layer of silicon nitride.
Claim 5
Dependent Claim 36 words
A MNOS transistor in accordance with claim 3 in which the silicon dioxide of the channel insulation is on the surface of the semiconductor body and the silicon nitride layer is on the silicon dioxide layer.
Claim 6
Dependent Claim 22 words
A MNOS transistor in accordance with claim 4 in which the silicon nitride layer is only as wide as the channel region.
Claim 7
Dependent Claim 20 words
A MNOS transistor in accordance with claim 5 including a strip of conductive polycrystalline silicon on the silicon nitride layer.
Claim 8
Dependent Claim 30 words
A MNOS transistor in accordance with claim 6 in which the channel region is of one conductivity type and the source and drain regions are of the opposite conductivity type.

References Cited (Backward Citations)

US3660819A Cited
US3738880A Cited
US3931632A Cited
US3893152A Cited
UST954008I4 Cited
US4123771A Cited
US3889287A Cited
US3836894A Cited
US4104675A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-04-05 1985-10-05 1986-04-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-04-05 1989-10-05 1990-04-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-04-05 1993-10-05 1994-04-06 $7700.00 Window Closed / Lapsed

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