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US4123771A Expired / Lapsed US ⏱️ 0.0 years remaining

Nonvolatile semiconductor memory

Assignee: Toshiba Corp
•
Filing: 1976-07-15
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Granted: 1978-10-31
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Expires: 1996-07-15
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Abstract

Abstract A nonvolatile semiconductor memory having an insulated gate field effect transistor whose structure is so made as to permit, during the write operation, a substrate surface region below the gate to be substantially enclosed by depletion layers extended from the source and drain regions or by said depletion layers and a channel formed between said regions, thereby increasing a resistance between the substrate and said substrate surface region to decrease the writing current in amount and the writing voltage in level.

Inventors

  • 👤 Yukimasa Uchida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 09:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 283 words
A metal-nitride-oxide semiconductor memory device comprising: a semiconductor n-type substrate; an elongated p-type source region in the surface of said substrate; an elongated p-type drain region in the surface of said substrate running parallel to said elongated source region; a first gate insulation film consisting of a very thin oxide film formed on a substrate surface region between said elongated source and drain regions; a silicon-nitride film formed on said first gate insulation film; first and second metal-oxide-semiconductor field-effect transistors, the source and drain of each of said transistors being said elongated source and drain regions, said transistors being positioned respectively on either side of said first gate insulation film and having respectively second and third gate insulation films between said elongated source and drain regions; source, drain, and first, second and third gate electrodes respectively formed on said elongated source and drain regions, and said first, second and third gate insulation films, said second and third gate electrodes being separated from said first gate electrode; means for effecting writing-in of information by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground potential to said substrate and to said first gate electrode and a predetermined negative potential to said source, drain and second and third gate electrodes so as to form a depletion layer which surrounds completely the substrate surface region under said first gate insulation film at the time of effecting writing-in of information; and means for allowing the potential of said substrate surface regions completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
Claim 2
Dependent Claim 283 words
A metal-nitride-oxide semiconductor memory device comprising: a semiconductor n-type substrate; an elongated p-type source region in the surface of said substrate; an elongated p-type drain region in the surface of said substrate running parallel to said elongated source region; a first gate insulation film consisting of a very thin oxide film formed on a substrate surface region between said elongated source and drain regions; a silicon-nitride film formed on said first gate insulation film; first and second metal-oxide-semiconductor field-effect transistors, the source and drain of each of said transistors being said elongated source and drain regions, said transistors being positioned respectively on either side of said first gate insulation film and having respectively second and third gate insulation films between said elongated source and drain regions; source, drain, and first, second and third gate electrodes respectively formed on said elongated source and drain regions, and said first, second and third gate insulation films, said second and third gate electrodes being separated from said first gate electrode; means for effecting writing-in of information by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground potential to said substrate and to said first gate electrode and a predetermined negative potential to said source, drain and second and third gate electrodes so as to form a depletion layer which surrounds completely the substrate surface region under said first gate insulation film at the time of effecting writing-in of information; and means for allowing the potential of said substrate surface regions completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
Claim 3
Dependent Claim 263 words
A metal-nitride oxide semiconductor memory device comprising: a semiconductor n-type substrate; an elongated p-type source region in the surface of said substrate; an elongated p-type drain region in the surface of said substrate running parallel to said elongated source region; a gate insulation film consisting of a very thin oxide film formed on a substrate surface region between said elongated source and drain regions; a silicon-nitride film formed on said gate insulation film; first and second electrode insulation films extending between said elongated source and drain regions, said first and second electrode insulation films being positioned respectively on either side of said gate insulation film; source, drain, gate, and first and second control electrodes respectively formed on said elongated source and drain regions, said gate and said first and second electrode insulation films, said first and second control electrodes being separated from said gate electrode; means for effecting writing-in of information by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground potential to said substrate and to said first gate electrode and a predetermined negative potential to said source, said drain and said first and second control electrodes so as to form a depletion layer which surrounds completely the substrate surface region under said gate insulation film at the time of effecting writing-in of information; and means for allowing the potential of said substrate surface regions completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
Claim 4
Dependent Claim 263 words
A metal-nitride oxide semiconductor memory device comprising: a semiconductor n-type substrate; an elongated p-type source region in the surface of said substrate; an elongated p-type drain region in the surface of said substrate running parallel to said elongated source region; a gate insulation film consisting of a very thin oxide film formed on a substrate surface region between said elongated source and drain regions; a silicon-nitride film formed on said gate insulation film; first and second electrode insulation films extending between said elongated source and drain regions, said first and second electrode insulation films being positioned respectively on either side of said gate insulation film; source, drain, gate, and first and second control electrodes respectively formed on said elongated source and drain regions, said gate and said first and second electrode insulation films, said first and second control electrodes being separated from said gate electrode; means for effecting writing-in of information by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground potential to said substrate and to said first gate electrode and a predetermined negative potential to said source, said drain and said first and second control electrodes so as to form a depletion layer which surrounds completely the substrate surface region under said gate insulation film at the time of effecting writing-in of information; and means for allowing the potential of said substrate surface regions completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.

References Cited (Backward Citations)

US3513364A Cited
US3345216A Cited
US3718916A Cited
US3868721A Cited
US3893151A Cited
US3868187A Cited
US3797000A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-10-30 1982-05-01 1982-10-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-10-30 1986-05-01 1986-10-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-10-30 1990-05-01 1990-10-31 $7700.00 Window Closed / Lapsed

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