Charge coupled digital-to-analog converter

Claim 1

A charge coupled digital-to-analog converter having a plurality of digital input lines with successive significance levels, and an analog output line, comprising: a body of semiconductor material of a first conductivity type and having a major surface including a plurality of integrated circuit elements; a first semiconductor region of a second conductivity type adjacent said major surface and extending from said surface to a predetermined depth into said body, said first region forming a plurality of channels in said semiconductor body through which charges can be caused to flow when said circuit elements are appropriately biased; sample gating means connected to said plurality of digital input lines for simultaneously sampling the digital input bits; said sample gating means comprising a transistor device implemented on said body of semiconductor materials having its conduction path connected between one of said digital input lines and a corresponding one of said plurality of channels in said body; a plurality of second semiconductor regions of said first conductivity type adjacent said major surface in each of said channels, said second region having a first conductivity type forming dopant concentration higher than that of said body; a plurality of input means connected to respective ones of said second semiconductor regions for applying a predetermined electric charge thereto; an ordered plurality of third semiconductor regions of said first conductivity type in said semiconductor body adjacent said major surface and located at the termination of said first plurality of channels, said third region having a first conductivity type forming dopant concentration higher than that of said body but less than that of said second semiconductor regions; said third semiconductor regions forming a plurality of storage wells, each of said storage wells functioning to store a predetermined amount of electronic charge in the form of a charge packet, the location of said storage wells and said amount of electronic charge being defined by the relative locations of a first edge formed by a single transfer gate overlying said body of semiconductor material, said single transfer gate including a plurality of notches, each notch corresponding to a different one of said storage wells, the normal projection of each notch into said semiconductor body defining a peripheral edge of said respective storage well; and a second substantially linear opposite edge, formed by a single backflow gate overlying said body of semiconductor material, said amount of electronic charge corresponding to the bit significance of the corresponding input bit lines; each of said ordered third semiconductor regions having a cross-sectional area measured in a plane parallel to said major surface which increases with each successive ordered region, the dimension of said area in which successive region increasing both in a direction parallel to said channel direction, and in a direction perpendicular to said channel direction; a fourth semiconductor region of said first conductivity type in said semiconductor body adjacent said major surface and disposed adjacent said third semiconductor region, said fourth region having a first conductivity type forming dopant concentration substantially the same as said second region; and biasing means to cause charge flow through said channels, said biasing means including first transfer means for transferring charge from each of said second semiconductor regions to respective ones of said third semiconductor regions during a first time interval until charge equilibrium has been established; and second transfer means for substantially simultaneously transferring charge from each of said third semiconductor regions to said fourth semiconductor region during a second subsequent time interval thereby accumulating the charge from all of said charge storage regions.