US4320464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary divider with carry-save adders
Assignee: Bank of America NA
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Filing: 1980-05-05
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Granted: 1982-03-16
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Expires: 2000-05-05
Abstract
Abstract A high-speed binary divider is provided which produces two quotient bits per processor cycle using two carry-save adders in a nonrestoring division mode with a delayed sign logic circuit selecting the adder having the required adder result for the current partial remainder.
Inventors
- 👤 Daniel J. Desmonds
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:46
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F2207/00; G06F2207/535; G06F2207/5352
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
276 words
A binary divider comprising: an enable register means for receiving a dividend, a register means for receiving a divisor, a generate register means, first and second carry-save adders, the first adder connected to receive inputs from said enable register, register means for receiving a divisor and generate register and the second adder connected to receive inputs from said enable register, the complement of the contents of said register means for receiving a divisor, and generate register, said first and second carry-save adders producing first and second possible partial remainders at each cycle of the division process, first and second means for determining the sign of the first and second possible partial remainders connected to said first and second adders, respectively, sign record flip-flop means for storing the sign of the partial remainder selected on the next preceding cycle of the division process, adder select gate means for gating the outputs of one of said adders to said enable register and to said generate register for a further cycle of the division process, said adder select gate means being connected with said sign record flip-flop means to provide the sign of the selected partial remainder at each cycle of the division process and to receive the stored sign of the preceding partial remainder and to receive an output from said first and second means for determining the sign of the possible partial remainder at each cycle of the division process to use in determining which of said adder outputs is to be gated, and a quotient shift register means connected to an output of said sign record flip-flop means for storing quotient bits as they are developed.
Claim 2
Dependent Claim
276 words
A binary divider comprising: an enable register means for receiving a dividend, a register means for receiving a divisor, a generate register means, first and second carry-save adders, the first adder connected to receive inputs from said enable register, register means for receiving a divisor and generate register and the second adder connected to receive inputs from said enable register, the complement of the contents of said register means for receiving a divisor, and generate register, said first and second carry-save adders producing first and second possible partial remainders at each cycle of the division process, first and second means for determining the sign of the first and second possible partial remainders connected to said first and second adders, respectively, sign record flip-flop means for storing the sign of the partial remainder selected on the next preceding cycle of the division process, adder select gate means for gating the outputs of one of said adders to said enable register and to said generate register for a further cycle of the division process, said adder select gate means being connected with said sign record flip-flop means to provide the sign of the selected partial remainder at each cycle of the division process and to receive the stored sign of the preceding partial remainder and to receive an output from said first and second means for determining the sign of the possible partial remainder at each cycle of the division process to use in determining which of said adder outputs is to be gated, and a quotient shift register means connected to an output of said sign record flip-flop means for storing quotient bits as they are developed.
Claim 3
Dependent Claim
66 words
The divider of claim 1 wherein said adder select gate means selects the contents of the first carry-save adder if the sign record flip-flop means is set and the sign of the possible partial remainder from the first carry-save adder is negative or if the sign record flip-flop means is clear and the sign of the possible partial remainder from the second carry-save adder is positive.
Claim 4
Dependent Claim
29 words
The divider of claim 2 wherein said adder select gate means selects the contents of the second carry-save adder as the complement function of the first carry-save adder selection.
Claim 5
Dependent Claim
169 words
A binary divider with carry-save adders comprising: a first carry-save adder, a first holding register connected to the first carry-save adder for holding the results of the first carry-save adder, a second carry-save adder, a second holding register connected to the second carry-save adder for holding the results of the second carry-save adder, first and second sign detection means for determining the sign of the operand in said first and second holding registers, respectively, means, connected with said first and second sign detection means, for selecting as a partial remainder the operand in one of said first and second carry-save adders and for producing the selected operand as an output, first, second, and third registers for holding input operands for said first and second carry-save adders, wherein said third register holds the divisor, and means for connecting said first, second and third registers to said first carry-save adder and said first and second registers and the complement of the contents of the third register to said second carry-save adder.
Claim 6
Dependent Claim
169 words
A binary divider with carry-save adders comprising: a first carry-save adder, a first holding register connected to the first carry-save adder for holding the results of the first carry-save adder, a second carry-save adder, a second holding register connected to the second carry-save adder for holding the results of the second carry-save adder, first and second sign detection means for determining the sign of the operand in said first and second holding registers, respectively, means, connected with said first and second sign detection means, for selecting as a partial remainder the operand in one of said first and second carry-save adders and for producing the selected operand as an output, first, second, and third registers for holding input operands for said first and second carry-save adders, wherein said third register holds the divisor, and means for connecting said first, second and third registers to said first carry-save adder and said first and second registers and the complement of the contents of the third register to said second carry-save adder.
Claim 7
Dependent Claim
25 words
The divider of claim 4 and wherein said means for selecting includes a sign record flip-flop to store the sign of the previous partial remainder.
Claim 8
Dependent Claim
64 words
The divider of claim 5 wherein said means for selecting selects the contents of the first carry-save adder as the correct partial remainder if the sign record flip-flop is set and the sign of the results from the first carry-save adder is negative or if the sign record flip-flop is clear and the sign of the results from the second carry-save adder is positive.
Claim 9
Dependent Claim
28 words
The divider of claim 6 wherein said means for selecting selects the contents of the second carry-save adder as the complement function of the first carry-save adder selection.
Claim 10
Dependent Claim
35 words
The divider of claim 7 and a quotient shift register means for storing quotient bits as they are developed, said quotient shift register means being connected to receive an output of said sign record flip-flop.
References Cited (Backward Citations)
US3223831A
Cited
US3293418A
Cited
US3319057A
Cited
US3621218A
Cited
US3591787A
Cited
US3733477A
Cited
US3852581A
Cited
US4084254A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-03-15 | 1985-09-14 | 1986-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-03-15 | 1989-09-14 | 1990-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-03-15 | 1993-09-14 | 1994-03-16 | $7700.00 | Window Closed / Lapsed |