Two bit binary divider

Claim 2

A 2-bit, non-restore, look-ahead, binary divider, comprising: means for subtracting a multiple of the divisor from four times the remainder for providing a new remainder in each cycle of operation; means for developing a tentative divisor multiplication factor in each cycle of operation and concurrently with the operation of said subtracting means, said developing means being tied to said subtracting means; means for correcting said tentative factor developed, concurrently with the operation of said subtracting means, said factor correcting means being connected to said tentative factor developing means; means for generating tentative bits of quotient in each cycle of operation, being connected to said factor correcting means; and means for correcting said tentative quotient bits generated in each operating cycle to corrected quotient bits, said quotient bit correcting means being connected with said tentative quotient bit generating means and said subtractiNg means.

Claim 3

Apparatus of claim 1 wherein said subtracting means includes: adder means for adding two values for providing a partial remainder and sign; first storage means including shift means for storing four times the partial remainder provided by said adder means, said first storage and shift means having its input tied to the remainder output of said adder means and its output tied to an input of said adder means; second storage means for providing a negative one times the divisor to said adder means at the initiation of the division operation, being connected to an input of said adder means; and third storage means including gating and sign changing means for providing a multiple of the divisor to said adder means said third means being connected on its input to said factor correcting means and on its output to an input to said adder means.

Claim 4

Apparatus for claim 1 wherein said developing means includes: means for temporarily holding partial remainder values said means being fed from said subtracting means; and decoder means for decoding partial remainder and divisor values for developing said tentative divisor multiplication factors, said decoder being connected to said temporary holding means.

Claim 5

Apparatus of claim 3, wherein said tentative quotient bit generating means includes: means for selectively choosing among predetermined bit values, said means being controlled by the output of said tentative factor correcting means; and means for storing said bit values selected, said storage means being connected to said selection means.

Claim 6

A 2 bit, non-restore, look-ahead binary divider comprising: a full propagate adder; a first register having an input connected to shift-left 2 bits a value entered from an output of said adder, said register input being connected to said adder output, said register output being connected to an input of said adder; a second register having its output tied to one of said adder inputs, said second register containing the divisor value; a third register having its output tied to an input of said adder; a first selection circuit having its output connected to the input of said third register, said first selection circuitry being input by one times the divisor and three times the divisor signals; a first decoder circuit, said decoder having its output connected to the input of said first selection circuitry; a second decoder circuit, said second decoder having its output connected to the input of said first decoder and being input by a divisor value; a fourth register having its output connected to said second decoder circuit and its input connected to said adder remainder output; a second selection circuit being tied on its inputs to said first decoder circuit; a fifth register being connected on its input to the output of said second selection circuit and on its output to an input of said first decoder circuit; and a third decoder circuit having an input each from the output of said fifth register, from an output of said first register and from an output of said adder.

Claim 7

A 2 bit, non-restore, look-ahead binary divider comprising: a full propagate adder; a first register having an input connected to shift-left 2 bits a value entered from an output of said adder, said register input being connected to said adder output, said register output being connected to an input of said adder; a second register having its output tied to one of said adder inputs, said second register containing the divisor value; a third register having its output tied to an input of said adder; a first selection circuit having its output connected to the input of said third register, said first selection circuitry being input by one times the divisor and three times the divisor signals; a first decoder circuit, said decoder having its output connected to the input of said first selection circuitry; a second decoder circuit, said second decoder having its output connected to the input of said first decoder and being input by a divisor value; a fourth register having its output connected to said second decoder circuit and its input connected to said adder remainder output; a second selection circuit being tied on its inputs to said first decoder circuit; a fifth register being connected on its input to the output of said second selection circuit and on its output to an input of said first decoder circuit; and a third decoder circuit having an input each from the output of said fifth register, from an output of said first register and from an output of said adder.

Claim 8

An iterative method of 2 bit, non-restore, look-ahead, binary division in a digital processor, incorporating the subtraction of a multiple of the divisor from four times the remainder wherein the dividend is the remainder for the initial iteration, comprising the steps of: examining with first decoding means the magnitudes of the divisor and the remainder from the preceding iteration to predict a tentative multiplication factor; adjusting with second decoding means said tentative multiplication factor based on feed back from the preceding iteration to produce a corrected multiplication factor; selecting with first selecting means a divisor multiple based upon the corrected multiplication factor produced; storing with storing means four times the remainder generated in the preceding operation; performing with adder mEans said subtraction; selecting with second selection means a tentative quotient based upon the corrected multiplication factor produced; correcting with third decoding means the tentative quotient bits based on the history of the sign change between the present and previous remainders; and entering with loading means said corrected quotient bits into a quotient register.

Claim 9

An iterative method of 2 bit, non-restore, look-ahead, binary division in a digital processor, incorporating the subtraction of a multiple of the divisor from four times the remainder wherein the dividend is the remainder for the initial iteration, comprising the steps of: examining with first decoding means the magnitudes of the divisor and the remainder from the preceding iteration to predict a tentative multiplication factor; adjusting with second decoding means said tentative multiplication factor based on feed back from the preceding iteration to produce a corrected multiplication factor; selecting with first selecting means a divisor multiple based upon the corrected multiplication factor produced; storing with storing means four times the remainder generated in the preceding operation; performing with adder mEans said subtraction; selecting with second selection means a tentative quotient based upon the corrected multiplication factor produced; correcting with third decoding means the tentative quotient bits based on the history of the sign change between the present and previous remainders; and entering with loading means said corrected quotient bits into a quotient register.