High speed divider

Claim 1

A HIGH SPEED PARALLEL DIVIDER FOR A DIGITAL COMPUTER COMPRISING A FIRST REGISTER MEANS FOR STORING MULTIPLES OF A DIVISOR AND A SECOND REGISTER MEANS FOR STORING A DIVIDEND, THE HIGHEST ORDER DIGITS OF SAID DIVIDEND BEING LOCATED IN THE HIGHEST ORDER BIT POSITIONS OF SAID SECOND REGISTER, A PLURALITY OF DIFFERENCE NETWORKS, A THIRD REGISTER MEANS, MEANS FOR SHIFTING A PLURALITY OF DIVIDEND BITS FORMING A PORTION OF SAID DIVIDEND FROM THE HIGHEST ORDER POSITIONS OF SAID SECOND REGISTER INTO THE LOWEST ORDER BIT POSITIONS OF SAID THIRD REGISTER AND SIMULTANEOUSLY SHIFTING THE REMAINDER OF SAID DIVIDEND INTO THE HIGHEST ORDER BIT POSITIONS OF SAID SECOND REGISTER; MEANS FOR APPLYING SAID PLURALITY OF DIVIDEND BITS IN SAID THIRD REGISTER TO EACH OF SAID DIFFERENCE NETWORKS AND MEANS FOR SIMULTANEOUSLY APPLYING EACH OF SAID DIVISOR MULTIPLES TO SEPARATE ONES OF SAID NETWORKS TO THEREBY PERFORM A PLURALITY OF TRIAL SUBTRACTIONS; SIGN SAMPLING MEANS ASSOCIATED WITH EACH OF SAID DIFFERENCE NETWORKS FOR DETERMINING THE SIGN OF EACH TRIAL SUBTRACTION; LOGIC MEANS RESPONSIVE TO SAID SIGNAL SAMPLING TO GENERATE, A PLURALITY OF PARTIAL QUOTIENT BITS, AND MEANS FOR APPLYING THE GENERATED PLURALITY OF PARTIAL QUOTIENT BITS TO THE LOWEST ORDER POSITIONS OF SAID SECOND REGISTER MEANS, AND MEANS TO SIMULTANEOUSLY SHIFT SAID PARTIAL QUOTIENT BITS TO HIGHER ORDER BIT POSITIONS OF SAID SECOND REGISTER ON SUBSEQUENT SHIFTING OF SAID DIVIDEND BITS.