Division system and method

Claim 2

A digital division system for dividing a dividend by a divisor comprising: table look-up means responsive to the divisor for generating a dIgital value M which, when multiplied against the divisor, provides a product approximating unity; means coupled to the table look-up means and responsive to the value M, the divisor and the dividend for generating new divisor and new dividend values; recirculating means coupled to the new divisor and new dividend value generating means and responsive to the new divisor and dividend values for initially utilizing the new dividend value as a remainder, and thereafter reducing the remainder through successive iterations, each iteration comprising the addition of a first portion of the previous remainder to the product of the new divisor value and a second portion of the previous remainder to form a new remainder; and means coupled to the recirculating means and responsive to the second portion of each remainder formed for providing a quotient value.

Claim 3

A digital division system for dividing a dividend by a divisor comprising: means responsive to the value of the divisor for generating a selected factor which, when multiplied against the divisor, provides a new divisor value approximating unity; multiplier means coupled to the means for generating and responsive to the divisor, the dividend and the selected factor for multiplying the divisor and dividend against the selected factor to provide new divisor and new dividend values; and means coupled to the multiplier means and responsive to the new divisor and new dividend values for successively generating new partial quotients and new remainder values in iterative fashion.

Claim 4

A digital division system for dividing a dividend by a divisor comprising: means responsive to the value of the divisor for generating a selected factor which, when multiplied against the divisor, provides a new divisor value approximating unity; multiplier means coupled to the means for generating and responsive to the divisor, the dividend and the selected factor for multiplying the divisor and dividend against the selected factor to provide new divisor and new dividend values; and means coupled to the multiplier means and responsive to the new divisor and new dividend values for successively generating new partial quotients and new remainder values in iterative fashion.

Claim 5

The invention as set forth in claim 2, wherein the means for successively generating new partial quotient values includes means responsive to each of a succession of new remainder values for selecting a predetermined number of higher order digits of each new remainder value as a new partial quotient.

Claim 6

The invention as set forth in claim 3 above, wherein said system in addition includes means coupled to the multiplier means and responsive to the new divisor value for generating a new small divisor, -Y, comprising the difference between the new divisor value and unity, wherein said new small divisor has a selected number of high order digits of zero value, and wherein said means for generating new partial quotients and new remainder values comprises second multiplier means coupled to the means for generating a new small divisor for providing the products of the new small divisor and the selected predetermined number of higher order digits of each new remainder value, and carry-save adder means coupled to the second multiplier means for combining the products with a predetermined number of lower order digits of each new remainder value to form the next new remainder value.

Claim 7

The invention as set forth in claim 4 above, wherein said system further includes quotient generating means including a pair of quotient registers, means coupled between the quotient registers and the carry-save adder means for inserting successive ones of the new partial quotients in selected positions in said quotient register means, and quotient adder means coupled to the quotient registers and responsive to the new partial quotients for generating a full quotient value.

Claim 8

The invention as set forth in claim 5 above, wherein said successive partial quotients are alternated between said registers in overlapping digital positions relative to the digital places in the full quotient value, and wherein said means for generating a selected factor comprises logic circuit table look-up circuits.

Claim 9

A digital division system responsive to divisor and dividend values to generate a quotient comprising: divisor register means for presenting the divisor value; dividend register means for presenting the dividend value; table look-up logic circuits coupled to the divisor register means and responsive to the divisor value to provide a digital value M which, when multiplied against the divisor value, provides a new divisor value in a predetermined range approximating unity, said range being no greater than unity at one extreme and having a selected number N of high order fractional binary 1 digits at the other extreme; first multiplier means coupled to the dividend register means and the table look-up logic circuits and responsive to the divisor and dividend values for generating the new divisor value, and a new dividend value, RO; subtraction circuit means coupled to the first multiplier means and responsive to the new divisor value for providing the difference, Y, between the new divisor value and unity as a new small divisor value; new small divisor register means coupled to the subtraction circuit means for presenting the new small divisor value; carry-save adder means including adder in gates coupled to the first multiplier means for providing the new dividend RO as an initial remainder value and thereafter successively adding partial products and low order digit values of prior remainder values to provide new remainder values; carry-save register means coupled to the carry-save adder means for receiving the successive remainder values from said carry-save adder means; quotient decoder means coupled to the carry-save register means for providing N high order digit values of each new remainder value; second multiplier means coupled to the new small divisor register means, the quotient decoder means and the adder in gates for multiplying the new small divisor value by the N high order digit values of each new remainder value to provide the partial products to the carry-save adder means; assimilator means coupled to the carry-save register means for assimilating N high order digit values of the successive remainder values; means, including a pair of quotient registers coupled to the assimilator means, for storing the successively provided digit values from the assimilator means as successive partial quotients in overlapping positions relative to a total quotient position; and quotient adder means coupled to the pair of quotient registers for providing a total quotient output value.

Claim 10

A digital division system responsive to divisor and dividend values to generate a quotient comprising: divisor register means for presenting the divisor value; dividend register means for presenting the dividend value; table look-up logic circuits coupled to the divisor register means and responsive to the divisor value to provide a digital value M which, when multiplied against the divisor value, provides a new divisor value in a predetermined range approximating unity, said range being no greater than unity at one extreme and having a selected number N of high order fractional binary 1 digits at the other extreme; first multiplier means coupled to the dividend register means and the table look-up logic circuits and responsive to the divisor and dividend values for generating the new divisor value, and a new dividend value, RO; subtraction circuit means coupled to the first multiplier means and responsive to the new divisor value for providing the difference, Y, between the new divisor value and unity as a new small divisor value; new small divisor register means coupled to the subtraction circuit means for presenting the new small divisor value; carry-save adder means including adder in gates coupled to the first multiplier means for providing the new dividend RO as an initial remainder value and thereafter successively adding partial products and low order digit values of prior remainder values to provide new remainder values; carry-save register means coupled to the carry-save adder means for receiving the successive remainder values from said carry-save adder means; quotient decoder means coupled to the carry-save register means for providing N high order digit values of each new remainder value; second multiplier means coupled to the new small divisor register means, the quotient decoder means and the adder in gates for multiplying the new small divisor value by the N high order digit values of each new remainder value to provide the partial products to the carry-save adder means; assimilator means coupled to the carry-save register means for assimilating N high order digit values of the successive remainder values; means, including a pair of quotient registers coupled to the assimilator means, for storing the successively provided digit values from the assimilator means as successive partial quotients in overlapping positions relative to a total quotient position; and quotient adder means coupled to the pair of quotient registers for providing a total quotient output value.

Claim 13

A binary digital system for developing new remainders from divisor values and prior remainders without carry propagation delay comprising: carry-save adder circuits coupled to receive a portion of each prior remainder and a new partial product for providing a new remainder in carry-save form therefrom; carry and sum register means coupled to said carry-save adder circuits for storing each new remainder; means coupling the carry and sum register means to the carry-save adder circuits to provide a less significant digit portion of each new remainder to the carry-save adder circuits as said portion of each prior remainder; quotient decoder circuits coupled to said carry and sum register means for deriving a more significant digit portion of each new remainder, said quotient decoder circuits generating shift control signals for the successive generation of the new partial products; and multiplier circuit means coupled to receive the divisor values, coupled to the quotient decoder circuits to receive the shift control signals, and coupled to the carry-save adder circuits for providing the new partial products to the carry-save adder circuits.

Claim 14

A binary digital system for developing new remainders from divisor values and prior remainders without carry propagation delay comprising: carry-save adder circuits coupled to receive a portion of each prior remainder and a new partial product for providing a new remainder in carry-save form therefrom; carry and sum register means coupled to said carry-save adder circuits for storing each new remainder; means coupling the carry and sum register means to the carry-save adder circuits to provide a less significant digit portion of each new remainder to the carry-save adder circuits as said portion of each prior remainder; quotient decoder circuits coupled to said carry and sum register means for deriving a more significant digit portion of each new remainder, said quotient decoder circuits generating shift control signals for the successive generation of the new partial products; and multiplier circuit means coupled to receive the divisor values, coupled to the quotient decoder circuits to receive the shift control signals, and coupled to the carry-save adder circuits for providing the new partial products to the carry-save adder circuits.