Buffer circuitry

Claim 2

Buffer circuitry comprising: first and second switching devices which each have a control terminal and output circuitry, the output circuitry of the devices being coupled together and being coupled to an output terminal of the buffer circuitry; the relative device sizes being such that the resistance of the first switching device being substantially greater than the resistance of the second switching device; a first inverter circuit having an input terminal which is coupled to a first input terminal of the buffer circuitry; a second inverter circuit having a first input terminal which is coupled to a second input terminal of the buffer circuitry and having a second input terminal which is coupled to the control terminal of the second switching device and to an output terminal of the first inverter circuit and having an output terminal which is coupled to the control terminal of the first switching device; and the first and second inverter circuits being configured to selectively control the first and second switching devices such that at the start of a cycle of operation the output terminal of the buffer circuitry essentially electrically floats in potential and then thereafter it first assumes a first logic level and then thereafter it stays at the first logic level if the first input terminal of the buffer is at the first logic level or it assumes a second logic level if the potential of the first input terminal is at the second logic level.

Claim 3

The buffer circuitry of claim 1 wherein each inverter circuit comprises a load element and a switching device having a control terminal and output circuitry.

Claim 4

The buffer circuitry of claim 2 wherein each load element comprises a switching device.

Claim 5

Buffer circuitry comprising: first, second, third, fourth, fifth, and sixth switching devices, each comprising a control terminal and output circuitry; first, second, third, and fourth inverter circuits, each comprising at least first and second input terminals and an output terminal; resistive circuit means; the first input terminal of the first inverter circuit being coupled to the first input terminal of the second inverter and being coupled to a first input terminal of the buffer circuitry; the output circuitry of the first switching device being coupled to a second input terminal of the buffer circuitry and to the second input terminals of the first and second inverter circuits; the output terminal of the first inverter circuit being coupled to the control terminal of the fourth switching device; the output terminal of the second inverter circuit being coupled to the control terminal of the fifth switching device, the first input terminals of the third and fourth inverter circuits, and resistive circuit means, and to the output circuitry of the sixth switching device; the output circuitry of the fourth and fifth switching devices being coupled to the output circuitry of the third switching device and to an output terminal of the buffer circuitry; the output terminal of the third inverter circuit being coupled to the control terminal of the third switching device; the output terminal of the fourth inverter circuit being coupled to the control terminal of the second switching device; the output circuitry of the second switching device being coupled to the second inverter circuit; and the control terminal of the sixth switching device being coupled to the second input terminals of the third and fourth inverter circuits and to a third buffer circuitry input terminal.

Claim 6

Buffer circuitry comprising: first, second, third, fourth, fifth, and sixth switching devices, each comprising a control terminal and output circuitry; first, second, third, and fourth inverter circuits, each comprising at least first and second input terminals and an output terminal; resistive circuit means; the first input terminal of the first inverter circuit being coupled to the first input terminal of the second inverter and being coupled to a first input terminal of the buffer circuitry; the output circuitry of the first switching device being coupled to a second input terminal of the buffer circuitry and to the second input terminals of the first and second inverter circuits; the output terminal of the first inverter circuit being coupled to the control terminal of the fourth switching device; the output terminal of the second inverter circuit being coupled to the control terminal of the fifth switching device, the first input terminals of the third and fourth inverter circuits, and resistive circuit means, and to the output circuitry of the sixth switching device; the output circuitry of the fourth and fifth switching devices being coupled to the output circuitry of the third switching device and to an output terminal of the buffer circuitry; the output terminal of the third inverter circuit being coupled to the control terminal of the third switching device; the output terminal of the fourth inverter circuit being coupled to the control terminal of the second switching device; the output circuitry of the second switching device being coupled to the second inverter circuit; and the control terminal of the sixth switching device being coupled to the second input terminals of the third and fourth inverter circuits and to a third buffer circuitry input terminal.

Claim 7

The buffer circuitry of claim 4 further comprising: capacitive circuit means; and a fifth inverter circuit having a first input terminal coupled to the first input terminal of the buffer circuitry and a second input terminal coupled to the second input terminal of the first inverter circuit and having an output terminal which is coupled to the second input terminal through the capacitive circuit means.

Claim 8

The buffer circuitry of claim 5 wherein: each inverter circuit comprises a separate pair of field effect transistors with the output circuitry of each of the two transistors being coupled to the other; and the resistive means is a depletion mode field effect transistor.

Claim 9

Buffer circuitry (100) comprising: a first switching device (T110) having a control terminal (260) and having output circuitry (160) adapted to be coupled to a first potential source (VCCO); a second switching device (T130) having a control terminal (220) and having output circuitry (180) adapted to be coupled to a second potential source (Vref0); the output circuitry of the first (T110) and second (T130) switching devices being coupled together and being coupled to an output terminal (AC0) of the buffer circuitry (100); first (T80, T90) and second (T140, T150, T160) circuit means coupled to the control terminals (220, 260) of the second (T130) and first (T110) switching devices, respectively, for controlling each device; the first circuit means (T80, T90) also being coupled to the second circuit means (T140, T150, T160) for selectively controlling the second circuit means (T140, T150, T160) so as to selectively control the first switching device (T110); first (DIO) and second (OEO) separate buffer circuitry (100) input terminals being coupled to the first (T80, T90) and second (T140, T150, T160) circuit means, respectively; the relative device sizes being such that the resistance of the first switching device being substantially greater than the resistance of the second switching device; and the first and second circuit means being configured to selectively control devices such that at the start of a cycle of operation the output terminal of the buffer circuitry essentially electrically floats in potential and then thereafter it assumes the first potential source level and then thereafter it stays at the first potential source level if a first input terminal of the buffer circuitry is set to the potential level of the first potential source or it assumes the potential level of the second potential source if the first input terminal of the buffer circuitry is set to the potential level of the second potential source.

Claim 10

Buffer circuitry (100) comprising: a first switching device (T110) having a control terminal (260) and having output circuitry (160) adapted to be coupled to a first potential source (VCCO); a second switching device (T130) having a control terminal (220) and having output circuitry (180) adapted to be coupled to a second potential source (Vref0); the output circuitry of the first (T110) and second (T130) switching devices being coupled together and being coupled to an output terminal (AC0) of the buffer circuitry (100); first (T80, T90) and second (T140, T150, T160) circuit means coupled to the control terminals (220, 260) of the second (T130) and first (T110) switching devices, respectively, for controlling each device; the first circuit means (T80, T90) also being coupled to the second circuit means (T140, T150, T160) for selectively controlling the second circuit means (T140, T150, T160) so as to selectively control the first switching device (T110); first (DIO) and second (OEO) separate buffer circuitry (100) input terminals being coupled to the first (T80, T90) and second (T140, T150, T160) circuit means, respectively; the relative device sizes being such that the resistance of the first switching device being substantially greater than the resistance of the second switching device; and the first and second circuit means being configured to selectively control devices such that at the start of a cycle of operation the output terminal of the buffer circuitry essentially electrically floats in potential and then thereafter it assumes the first potential source level and then thereafter it stays at the first potential source level if a first input terminal of the buffer circuitry is set to the potential level of the first potential source or it assumes the potential level of the second potential source if the first input terminal of the buffer circuitry is set to the potential level of the second potential source.

Claim 11

Buffer circuitry having at least two input terminals and one output terminal comprising: first and second switching devices each having a control terminal and output circuitry, the output circuitry of both devices being coupled to the output terminal; first and second inverter circuits each having an input terminal coupled to a separate one of the input terminals of the buffer circuitry and each having an output terminal coupled to a separate control terminal of one of the switching devices; the second inverter circuit having a second input terminal coupled to the output terminal of the first inverter circuit; the relative device sizes being such that the resistance of the first switching device being substantially greater than the resistance of the second switching device; and the first and second inverter circuits being configured to selectively control the first and second switching devices such that at the start of a cycle of operation the output terminal of the buffer circuitry essentially electrically floats in potential and then thereafter it assumes a first logic level and then thereafter it stays at the first logic level if the first input terminal of the buffer is at the first logic level or it assumes a second logic level if the potential of the first input terminal is at the second logic level.

Claim 12

Buffer circuitry having at least two input terminals and one output terminal comprising: first and second switching devices each having a control terminal and output circuitry, the output circuitry of both devices being coupled to the output terminal; first and second inverter circuits each having an input terminal coupled to a separate one of the input terminals of the buffer circuitry and each having an output terminal coupled to a separate control terminal of one of the switching devices; the second inverter circuit having a second input terminal coupled to the output terminal of the first inverter circuit; the relative device sizes being such that the resistance of the first switching device being substantially greater than the resistance of the second switching device; and the first and second inverter circuits being configured to selectively control the first and second switching devices such that at the start of a cycle of operation the output terminal of the buffer circuitry essentially electrically floats in potential and then thereafter it assumes a first logic level and then thereafter it stays at the first logic level if the first input terminal of the buffer is at the first logic level or it assumes a second logic level if the potential of the first input terminal is at the second logic level.

Claim 13

Buffer circuitry comprising: the series combination of a pull-up switching device and a pull-down switching device with an output terminal coupled therebetween; the resistance of the pull-up switching device being substantially greater than the resistance of the pull-down switching device; first circuit means coupled to a control terminal of the pull-up device for selectively biasing the pull-up device on so as to allow the output terminal to assume a first output voltage state (logic level); second circuit means coupled to a control terminal of the pull-down device and to the first circuit means for maintaining the pull-down device biased off while the output terminal is assuming the first output voltage level (logic state) and for then biasing the pull-down device off if essentially the same logic state is applied to an input terminal of the second circuit means and for biasing the pull-down device on and causing the pull-up device to be biased off so as to allow the output terminal to assume a second voltage level (logic state) if, and only if, said second logic state is applied to the input terminal of the second circuit means; and the first and second circuit means being adapted to allow the output terminal of the buffer circuitry to selectively electrically float in potential.

Claim 14

Buffer circuitry comprising: the series combination of a pull-up switching device and a pull-down switching device with an output terminal coupled therebetween; the resistance of the pull-up switching device being substantially greater than the resistance of the pull-down switching device; first circuit means coupled to a control terminal of the pull-up device for selectively biasing the pull-up device on so as to allow the output terminal to assume a first output voltage state (logic level); second circuit means coupled to a control terminal of the pull-down device and to the first circuit means for maintaining the pull-down device biased off while the output terminal is assuming the first output voltage level (logic state) and for then biasing the pull-down device off if essentially the same logic state is applied to an input terminal of the second circuit means and for biasing the pull-down device on and causing the pull-up device to be biased off so as to allow the output terminal to assume a second voltage level (logic state) if, and only if, said second logic state is applied to the input terminal of the second circuit means; and the first and second circuit means being adapted to allow the output terminal of the buffer circuitry to selectively electrically float in potential.