Bipolar inverter and NAND logic circuit with extremely low DC standby power

Claim 2

An inverter circuit comprising: at least a single bipolar switchable transistor, a first region of which is connected to a given potential and a second region of which is connected to a potential different from said given potential, a load device interposed between said potential different from said given potential and said second region, an output terminal connected to said second region and said load device, an input terminal connected to a third region of said transistor, a source of standby current of one polarity connected to said third region of said transistor for maintaining said transistor in a conductive state when rendered conductive by a signal applied to said input terminal, diode means connected between said source of standby current and said input terminal for shunting said source to said given potential when said transistor is rendered nonconductive and said diode means is rendered conductive by another signal applied to said input and, means connected to said third region of said transistor and said input terminal for augmenting said standby current when said signal is applied to said input terminal.

Claim 3

An inverter circuit according to claim 1 wherein said first region is the emitter of said transistor said second region is the collector of said transistor and said third region is the base of said transistor.

Claim 4

An inverter circuit according to claim 2 wherein the diode formed by said base and said emitter of said transistor has a given switching point and said transistor has a given input capacitance.

Claim 5

An inverter circuit according to claim 3 wherein said diode has a switching point which is lower than said given switching point of said diode formed by said base and said emitter of said transistor.

Claim 6

An inverter circuit according to claim 3 wherein said means for augmenting said standby current of one polarity is a capacitor, the charge on which is changed when said transistor is rendered conductive.

Claim 7

An inverter circuit according to claim 5 wherein said capacitor has a capacitance greater than said given input capacitance.

Claim 8

An inverter circuit according to claim 1 wherein said load device is another bipolar switchable transistor.

Claim 9

An inverter circuit according to claim 7 wherein said another bipolar switchable transistor is the complement of said switchable transistor and wherein a first region of said another bipolar switchable transistor is connected to said potential different from said given potential, a second region of said another bipolar switchable device is connected to said output terminal and said third region of said another bipolar device is connected to said input terminal, a source of standby current of a second polarity connected to said third region of said another transistor for maintaining said another transistor in a conductive state when rendered conductive by said another signal applied to said input terminal, means connected between said source of standby current of a second polarity and said input terminal for shunting said source of standby current of a second polarity to the potential level of said signal when said another transistor is rendered nonconductive by said signal applied to said input, and, means connected to said third region of said another transistor and said input terminal for augmenting said standby current of second polarity when said another signal is applied to said input terminal.

Claim 10

An inverter circuit according to claim 8 wherein said first region is the emitter of said another transistor, said second region is the collector of said another transistor and said third region is the base of said another transistor.

Claim 11

An inverter circuit according to claim 9 wherein the diode formed by the base and emitter of said another transistor has a given switching point and said another transistor has a given input capacitance.

Claim 12

An inverter circuit according to claim 10 wherein said means for shunting said source of standby current of a second polarity to said potential level of said signal is a diode which is rendered conductive by the application of said signal applied to said input.

Claim 13

An inverter circuit according to claim 10 wherein said means for augmenting said standby current of second polarity is a capacitor, the charge on which is changed when said another transistor is rendered conductive.

Claim 14

An inverter circuit according to claim 11 wherein said diode has a switching point which is lower than said given switching of said diode formed by said base and said emitter of said another transistor.

Claim 15

An inverter circuit according to claim 12 wherein said capacitor has a capacitance greater than said given input capacitance of said another transistor.

Claim 16

An inverter circuit according to claim 1 wherein said means for augmenting said standby current of one polarity is a capacitor, the charge on which is changed when said transistor is rendered conductive.

Claim 17

An inverter circuit according to claim 1 further including means connected to said input terminal for applying said signal and said another signal to said inverter circuit.

Claim 18

A logic circuit comprising: a first pair of bipolar switchable transistors connected in series a first region of one of said first pair being connected to a given potential, a second pair of bipolar switchable transistors which are the complements of said first pair of transistors connected in parallel, first regions of which are connected to a potential different from said given potential and second regions of which are connected to a second given region of another of said first pair, a first region of said another of said first pair being connected to a second region of said one of said first pair, an output terminal connected to said second regions of said second pair of transistors and to said second region of said another of said first pair, a first input terminal connected to a third region of said one of said first pair of transistors and to a third region of one of said second pair input terminal connected to a third region of said another of said first pair of transistors and to a third region of another of said second pair of transistors, a source of standby current of a first polarity connected to each of said third regions of said first pair of transistors for maintaining said transistors in a conductive state when rendered conductive by a signal applied to said first and second inputs terminals, a source of standby current of a second polarity connected to each of said third regions of said second pair of transistors for maintaining said transistors in a conductive state when rendered conductive by another signal applied to said first and second input terminals, means connected between each of said sources of standby current and said input terminals for shunting said sources of standby current of said first and second polarity to said given potential and to the level of said signal, respectively, when said signal or said another signal applied to any of said transistors of said first and second pairs of transistors renders any of them nonconductive, and, means connected in parallel with each said means for shunting for augmenting said standby current of one polarity and said standby current of second polarity when the application of said signal or said another signal to said third regions of said first and second pairs of transistors renders any of said transistors conductive.

Claim 19

A logic circuit comprising: a first pair of bipolar switchable transistors connected in series a first region of one of said first pair being connected to a given potential, a second pair of bipolar switchable transistors which are the complements of said first pair of transistors connected in parallel, first regions of which are connected to a potential different from said given potential and second regions of which are connected to a second given region of another of said first pair, a first region of said another of said first pair being connected to a second region of said one of said first pair, an output terminal connected to said second regions of said second pair of transistors and to said second region of said another of said first pair, a first input terminal connected to a third region of said one of said first pair of transistors and to a third region of one of said second pair input terminal connected to a third region of said another of said first pair of transistors and to a third region of another of said second pair of transistors, a source of standby current of a first polarity connected to each of said third regions of said first pair of transistors for maintaining said transistors in a conductive state when rendered conductive by a signal applied to said first and second inputs terminals, a source of standby current of a second polarity connected to each of said third regions of said second pair of transistors for maintaining said transistors in a conductive state when rendered conductive by another signal applied to said first and second input terminals, means connected between each of said sources of standby current and said input terminals for shunting said sources of standby current of said first and second polarity to said given potential and to the level of said signal, respectively, when said signal or said another signal applied to any of said transistors of said first and second pairs of transistors renders any of them nonconductive, and, means connected in parallel with each said means for shunting for augmenting said standby current of one polarity and said standby current of second polarity when the application of said signal or said another signal to said third regions of said first and second pairs of transistors renders any of said transistors conductive.

Claim 20

A logic circuit according to claim 17 wherein said first regions, said second regions and said third regions are emitters, collectors and bases, respectively, of said transistors.

Claim 21

A logic circuit according to claim 18 further including means connected to said input terminals for applying said signal and said another signal to said logic circuit.

Claim 22

A logic circuit according to claim 18 wherein said means for shunting said sources of standby current of said first and second polarity to said given potential and to said level of said signal, respectively, are first and second diodes which are rendered conductive by the application of said another signal and said signal, respectively, to said input.

Claim 23

A logic circuit according to claim 20 wherein the diodes formed by said bases and said emitters of said transistors have a given switching point.

Claim 24

A logic circuit according to claim 21 wherein said first and second diodes have a switching point which is lower than said given switching point of said diodes formed by said bases and said emitters of said transistors.

Claim 25

A logic circuit according to claim 18 wherein said means for augmenting said standby current of one polarity and said standby current of a second polarity is a capacitor, the charge on which is changed when said transistors are rendered conductive.

Claim 26

A logic circuit according to claim 23 wherein transistors have a given input capacitance.

Claim 27

A logic circuit according to claim 24 wherein said capacitor has a capacitance which is greater than said given input capacitance.