Transistor logic circuit with upset feedback

Claim 2

A switching circuit arrangement comprising: a. at least one semiconductor device having an input and output means; b. means for applying a signal to said input means, said device being placed by said signal in a steady-state ON or in the alternative in a steady-state OFF condition, said device being momentarily placed in a transitory state by said signal when said device is switched from the steady-state ON to the steady-state OFF and from the steady-state OFFto the steady-state ON; c. feedback means coupled from said output means to said input means; d. said feedback means transmitting a degenerative signal from said output means to said input means after said signal places said device in said steady-state condition; e. said degenerative signal placing said input means at a voltage level for preventing said device from conducting into saturation after said signal places said device in the steadystate ON condition; f. said degenerative signal further placing said input means at a voltage near its conduction state after said signal places said device in the steady-state OFF condition; g. said feedback means in addition transmitting a regenerative signal from said output means to said input means after said signal places said device in said transitory condition; h. said regenerative signal applying a voltage to said input means to place it at a level to cause said device to rapidly switch to the steady-state ON condition.

Claim 3

The circuit in accordance with claim 1 wherein a logical circuit arrangement comprising an AND gate and an OR gate is connected to said input means.

Claim 4

The circuit in accordance with claim 1 wherein said semiconductor device is an NPN- or, in the alternative, a PNP-transistor.

Claim 5

A switching circuit arrangement comprising a. at least first and second semiconductor devices which are coupled to onE another, said first device which has an input means being operated in the common emitter and said second device being operated in the emitter follower mode; b. means for applying a signal to said first device; said first device being placed by said signal in a steady-state ON condition and said second device being placed in the steady-state OFF condition, and in the alternative, said signal placing said first device in a steady-state OFF condition and said second device in the steady-state ON condition, said devices being momentarily placed in a transitory state by said signal when said device is switched from the steady-state ON to the steady-state OFF and from the steady-state OFF to the steady-state ON; c. feedback means coupled from said second to said first semiconductor; d. said feedback means transmitting a degenerative signal from said second device to said first device after said signal places said devices in a steady-state condition; e. said degenerative signal placing said input means at a voltage level for preventing said device from conducting into saturation after said signal places said first device in a steady-state ON condition; f. said degenerative signal further placing said first device near its conduction level after said signal places said first device in the steady-state OFF condition; g. said feedback means in addition transmitting a regenerative signal from said second device to said first device after said signal places said devices in said transitory condition; h. said regenerative signal applying a voltage to said input means to place it at a level to cause said device to rapidly switch to the steady-state ON condition.

Claim 6

A switching circuit arrangement comprising a. at least first and second semiconductor devices which are coupled to onE another, said first device which has an input means being operated in the common emitter and said second device being operated in the emitter follower mode; b. means for applying a signal to said first device; said first device being placed by said signal in a steady-state ON condition and said second device being placed in the steady-state OFF condition, and in the alternative, said signal placing said first device in a steady-state OFF condition and said second device in the steady-state ON condition, said devices being momentarily placed in a transitory state by said signal when said device is switched from the steady-state ON to the steady-state OFF and from the steady-state OFF to the steady-state ON; c. feedback means coupled from said second to said first semiconductor; d. said feedback means transmitting a degenerative signal from said second device to said first device after said signal places said devices in a steady-state condition; e. said degenerative signal placing said input means at a voltage level for preventing said device from conducting into saturation after said signal places said first device in a steady-state ON condition; f. said degenerative signal further placing said first device near its conduction level after said signal places said first device in the steady-state OFF condition; g. said feedback means in addition transmitting a regenerative signal from said second device to said first device after said signal places said devices in said transitory condition; h. said regenerative signal applying a voltage to said input means to place it at a level to cause said device to rapidly switch to the steady-state ON condition.

Claim 7

The circuit in accordance with claim 4 wherein a logical circuit arrangement comprising an AND gate and an OR gate is connected to said input means.

Claim 8

A signal translating circuit comprising: a. a first and second transistor device, each comprising an emitter electrode, a base electrode, and a collector electrode; b. a signal input circuit coupled to the base electrode of said first transistor device; c. a switchable signal source coupled to said signal input circuit, said signal source capable of producing two separate and distinct input voltages; d. a signal output circuit coupled to the emitter electrode of said second transistor device; e. first coupling means coupled between the base electrode of said second transistor device and the collector electrode of said first transistor device; f. said emitter of said first transistor and said collector of said second transistor being coupled to potential sources; g. second coupling means comprising a first resistor coupled between the emitter electrode of said second transistor device and the base electrode of said first transistor device to provide a path for first and second feedback types; h. said first type of feedback existing between said first and second transistor devices via said second coupling means when said signal source is producing either of said input voltages and i. a second type of feedback existing between said first and second transistor devices via said second coupling means for a period of time following the switching of said signal source from one to the other of said two input voltages.

Claim 9

A signal translating circuit comprising: a. a first and second transistor device, each comprising an emitter electrode, a base electrode, and a collector electrode; b. a signal input circuit coupled to the base electrode of said first transistor device; c. a switchable signal source coupled to said signal input circuit, said signal source capable of producing two separate and distinct input voltages; d. a signal output circuit coupled to the emitter electrode of said second transistor device; e. first coupling means coupled between the base electrode of said second transistor device and the collector electrode of said first transistor device; f. said emitter of said first transistor and said collector of said second transistor being coupled to potential sources; g. second coupling means comprising a first resistor coupled between the emitter electrode of said second transistor device and the base electrode of said first transistor device to provide a path for first and second feedback types; h. said first type of feedback existing between said first and second transistor devices via said second coupling means when said signal source is producing either of said input voltages and i. a second type of feedback existing between said first and second transistor devices via said second coupling means for a period of time following the switching of said signal source from one to the other of said two input voltages.

Claim 10

The signal translating circuit in accordance with claim 6 where said first and second transistor devices are NPN-transistors each having a base, emitter and collector electrode and wherein, a. a first bias means is coupled to the base electrode of said first transistor device, and b. a second bias means is coupled to the emitter electrode of said first transistor, c. said first and second biasing means biasing said first transistor device in a relatively non-conducting state, d. third biasing means coupled to the emitter electrode of said second transistor device to bias it in a relatively conducting sTate.

Claim 11

The circuit in accordance with claim 7 wherein third coupling means comprising a second resistor are coupled between said base electrode of said first first transistor device and said third biasing means, whereby a first type of feedback exists between said first and second transistor devices via said third coupling means when said signal source is producing either of said input voltages and a second type of feedback exists between said first and second transistor devices via said third coupling means for a period of time following the switching of said signal source from one to the other of said two input voltages.

Claim 12

A signal translating circuit comprising: a. first and second NPN-transistor devices, each transistor device having a base electrode, a collector electrode and an emitter electrode; b. first bias means coupled to the collector electrode of said first transistor device, c. second bias means coupled to the base electrode of said first transistor device, d. said first and second biasing means biasing said first transistor device in a relatively non-conducting state; e. first coupling means including a resistor coupled between the collector and base electrodes of said first transistor device to prevent said first transistor means from being operated in a saturated condition; f. third biasing means coupled to the collector electrode of said second transistor device; g. fourth biasing means coupled to the emitter electrode of said second transistor device; h. said third and fourth biasing means biasing said second transistor device in a relatively conducting state; i. a signal input circuit coupled to the base electrode of said first transistor device; j. a switchable signal source coupled to said signal input circuit, said signal source being capable of producing two separate and distinct input voltages; k. a signal output circuit coupled to the emitter electrode of said second transistor device; l. second coupling means coupled between the collector electrode of said first transistor device and the base electrode of said second transistor device; m. third coupling means including a further resistor coupled between the emitter electrode of said second transistor device and the base electrode of said first transistor device, whereby a first type of feedback exists between said first and second transistor devices via said third coupling means when said signal source is producing either of said input voltages and a second type of feedback exists between said first and second transistor devices via said third coupling means for a period of time following the switching of said signal source from one to the other of said two input voltages.

Claim 13

A signal translating circuit comprising: a. first and second NPN-transistor devices, each transistor device having a base electrode, a collector electrode and an emitter electrode; b. first bias means coupled to the collector electrode of said first transistor device, c. second bias means coupled to the base electrode of said first transistor device, d. said first and second biasing means biasing said first transistor device in a relatively non-conducting state; e. first coupling means including a resistor coupled between the collector and base electrodes of said first transistor device to prevent said first transistor means from being operated in a saturated condition; f. third biasing means coupled to the collector electrode of said second transistor device; g. fourth biasing means coupled to the emitter electrode of said second transistor device; h. said third and fourth biasing means biasing said second transistor device in a relatively conducting state; i. a signal input circuit coupled to the base electrode of said first transistor device; j. a switchable signal source coupled to said signal input circuit, said signal source being capable of producing two separate and distinct input voltages; k. a signal output circuit coupled to the emitter electrode of said second transistor device; l. second coupling means coupled between the collector electrode of said first transistor device and the base electrode of said second transistor device; m. third coupling means including a further resistor coupled between the emitter electrode of said second transistor device and the base electrode of said first transistor device, whereby a first type of feedback exists between said first and second transistor devices via said third coupling means when said signal source is producing either of said input voltages and a second type of feedback exists between said first and second transistor devices via said third coupling means for a period of time following the switching of said signal source from one to the other of said two input voltages.

Claim 14

A signal translating circuit in accordance with claim 7 wherein said first and second transistor devices are PNP-types and a. said first bias means is coupled to the base electrodes of said first and second transistor devices; and b. said second bias means is coupled to the emitter electrode of said first transistor device and c. said first and second bias means biasing said first transistor device in a relatively non-conducting state; and d. third biasing means coupled to the emitter electrode of said second transistor device, e. said first and third biasing means biasing said second transistor device in a relatively conducting state; f. a signal input circuit coupled to the base electrode of said first transistor device; g. a switchable signal source coupled to said signal input circuit and said signal source capable of producing two separate and distinct input voltages; h. a signal output circuit coupled to the emitter electrode of said second transistor device; i. said first coupling means coupling the collector electrode of said first transistor device to the base electrode of said second transistor device; and j. fourth biasing means coupled to collEctor electrode of said second transistor device to limit the conduction thereof; k. impedance means comprising a first and a second resistor coupled in series and coupled between said third biasing means and said emitter electrode of said second transistor device; l. said second coupling means including a third resistor coupled to the coupling point of said first and second resistors and the base electrode of said first base electrode of said first transistor device, whereby a first type of feedback exists between said first and second transistor devices via said second coupling means when said signal source is producing either of said input voltages and a second type of feedback exists between said first and second transistor devices via said second coupling means when said signal source is producing either of said input voltages and a second type of feedback exists between said first and second transistor devices via said second coupling means for a period of time following the switching of said signal source from one to the other of said two input voltages.

Claim 15

The signal translating circuit as defined in claim 10 wherein said fourth biasing means is provided by coupling said collector electrode of said second transistor device to said first biasing means whereby said second transistor device is prevented from oscillating.