Limiting amplifier

Claim 1

A PEAK-DETECTING, LIMITING AMPLIFIER COMPRISING, FIRST AND SECOND TRANSISTORS EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, AN INPUT TERMINAL, A FIRST CAPACITOR CONNECTED BETWEEN SAID INPUT TERMINAL AND THE BASE OF SAID FIRST TRANSISTOR, FIRST AND SOURCES OF POTENTIAL FIRST AND SECOND RESISTORS RESPECTIVELY CONNECTED BETWEEN THE COLLECTOR ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS AND SAID FIRST SOURCE OF POTENTIAL, A DIRECT CONNECTION FROM THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR, A THIRD RESISTOR CONNECTED BETWEEN THE COLLECTOR AND A BASE ELECTRODES OF SAID FIRST TRANSISTOR, MEANS CONNECTING THE EMITTER ELECTRODE OF SAID FIRST TRANSISTOR TO A POINT OF REFERENCE POTENTIAL, A NETWORK INCLUDING A FOURTH RESISTOR CONNECTED BETWEEN THE EMITTER OF SAID SECOND TRANSISTOR AND SAID SECOND SOURCE OF POTENTIAL, A SECOND CAPACITOR AND A FIFTH RESISTOR CONNECTED IN SERIES IN THE NAMED ORDER BETWEEN THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR AND SAID SECOND SOURCE OF POTENTIAL, AND A DIODE CONNECTED FROM THE JUNCTION OF SAID SECOND CAPACITOR AND SAID FIFTH RESISTOR TO SAID POINT OF REFERENCE POTENTIAL, A VOLTAGE DIVIDER CONNECTED BETWEEN SAID FIRST AND SECOND OF POTENTIAL, AN OUTPUT TERMINAL CONNECTED TO A POINT ON SAID VOLTAGE DIVIDER, MEANS CONNECTING SAID OUTPUT TERMINAL TO A TRIGGER CIRCUIT, A THIRD CAPACITOR CONNECTED BETWEEN THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR AND SAID OUTPUT TERMINAL, AND A RESISTIVE FEEDBACK PATH CONNECTED BETWEEN THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR AND THE BASE ELECTRODE OF SAID FIRST TRANSISTOR.