Fabrication of complementary bipolar transistors and CMOS devices with poly gates

Claim 2

In a process for fabricating an integrated circuit in a substrate having high performance, complementary bipolar transistors and complementary insulated gate field effect transistors including base, emitter, source and drain regions, collector, base and body contact regions, gate oxide, gate structure and device contacts the improvement comprising: depositing N conductivity type impurities through openings in oxide mask layer to form emitter regions of an NPN bipolar transistors and N contact regions as the last device region forming step; removing portions of said oxide mask layer to expose the channel of said field effect transistors; forming a gate insulator layer on said substrate; forming a layer of doped polycrystalline silicon on said gate insulator layer immediately after forming said gate insulator layer; delineating said polycrystalline silicon layer to define field effect transistor gate structures and first level interconnects; depositing by chemical vapor deposition a layer of phosphorous doped silicon oxide; removing portions of said chemically vapor deposed layer to expose portions of said polycrystalline layer and portions of said oxide mask to expose portions of said substrate; and depositing and delineating a metallic layer to form second level interconnects and contacts.

Claim 3

The process according to claim 1 including etching said oxide mask layer after depositing said N conductivity type impurities to remove the topmost impurity containing portion of said oxide mask.

Claim 4

The process according to claim 1 including forming oxide in said openings in said oxide mask after depositing said N conductivity type impurities.

Claim 5

The process according to claim 1 wherein said gate insulator layer is formed to have a thickness of at least 1300 angstroms.

Claim 6

The process according to claim 4 wherein said doped polycrystalline silicon layer is formed by forming a layer of undoped polycrystalline silicon and subsequently doping said layer with phosphorous.

Claim 7

The process according to claim 1 including heating said chemical vapor deposited layer to a high temperature environment to cause flow of said layer and subsequently doping said reflowed layer with phosphorous.

Claim 8

The process according to claim 6 wherein said high temperature environment is a steam environment at a temperature in the range of 850° C. to 900° C.

Claim 9

The process according to claim 1 including forming a diffusion barrier layer on the backside of the substrate before introducing said N conductivity type impurities.

Claim 10

The process according to claim 1 including depositing P conductivity type impurities through openings in said oxide mask layer to form PNP emitter regions and P contact regions, and forming oxide in said openings in said oxide mask before depositing said N conductivity type impurities.

Claim 11

The process according to claim 1 wherein the steps performed after depositing the N conductivity type impurities are performed at a temperature below 1000° centigrade.

Claim 12

A process for simultaneously fabricating high voltage, high performance NPN, PNP and P and N channel MOS devices in dielectrically isolated islands comprising: introducing P conductivity type impurities into selected N conductivity type substrate regions having an impurity concentration of approximately 1×10 15 carriers per cubic centimeter to form a collector region of the PNP and body of an N channel MOS having a surface impurity concentration of approximately 1×10 16 carriers per cubic centimeter; introducing N conductivity type impurities into said P type collector region to form an N type base region and into said P type body to form N type source and drain regions having a surface impurity concentration of approximately 3×10 18 carriers per cubic centimeter; introducing P conductivity type impurities into selected N conductivity type substrate regions to form a base region of the NPN and source and drain regions of a P channel MOS having a surface impurity concentration of approximately 5×10 18 carriers per cubic centimeter; introducing P conductivity type impurities into N conductivity type base regions and selected P conductivity type regions to form emitter regions and contact regions respectively having a surface impurity concentration of approximately 2×10 20 carriers per cubic centimeter; introducing N conductivity type impurities into P conductivity type base regions and selected N conductivity type regions to form emitter regions and contact regions respectively having a surface impurity concentration of approximately 1×10 21 carriers per cubic centimeter; and forming gate oxide and gate electrode structure for the N and P channel MOS devices.

Claim 13

A process for simultaneously fabricating high voltage, high performance NPN, PNP and P and N channel MOS devices in dielectrically isolated islands comprising: introducing P conductivity type impurities into selected N conductivity type substrate regions having an impurity concentration of approximately 1×10 15 carriers per cubic centimeter to form a collector region of the PNP and body of an N channel MOS having a surface impurity concentration of approximately 1×10 16 carriers per cubic centimeter; introducing N conductivity type impurities into said P type collector region to form an N type base region and into said P type body to form N type source and drain regions having a surface impurity concentration of approximately 3×10 18 carriers per cubic centimeter; introducing P conductivity type impurities into selected N conductivity type substrate regions to form a base region of the NPN and source and drain regions of a P channel MOS having a surface impurity concentration of approximately 5×10 18 carriers per cubic centimeter; introducing P conductivity type impurities into N conductivity type base regions and selected P conductivity type regions to form emitter regions and contact regions respectively having a surface impurity concentration of approximately 2×10 20 carriers per cubic centimeter; introducing N conductivity type impurities into P conductivity type base regions and selected N conductivity type regions to form emitter regions and contact regions respectively having a surface impurity concentration of approximately 1×10 21 carriers per cubic centimeter; and forming gate oxide and gate electrode structure for the N and P channel MOS devices.

Claim 14

The process according to claim 11 wherein said first mentioned P type impurity introduction is performed by ion implantation and diffusion.

Claim 15

The process according to claim 12 wherein the remainder of the impurity introductions are performed by deposition.

Claim 16

The process according to claim 13 wherein the first mentioned N-type and second mentioned P-type impurity introduction include diffusion, and said second mentioned N-type and third mentioned P-type impurity introduction do not include a distinct diffusion step.

Claim 17

The process according to claim 11 wherein the backside of the substrate is covered by a protective layer before the second mentioned N impurity introduction.

Claim 18

The process according to claim 11 wherein said second mentioned P type impurity introduction is performed to form a junction of approximately 1.8 microns.