Method for fabricating semiconductor structure having complementary devices

Claim 2

In a method for making complementary circuitry having compatible voltage ratings for deviced formed therein, utilizing a semiconductor body having a region of N conductivity type and having first and second spaced generally parallel surfaces, forming a deep diffused region of P conductivity type in said semiconductor body extending inwardly from said second surface to a depth ranging from 15 to 80 microns by diffusing a P-type impurity into said semiconductor body for a period of time ranging from 8 hours to 100 hours at a temperature ranging from 1,200* to 1,300* C to provide a P-N junction extending to said second surface, said step of forming the deep diffused region being performed prior to the formation of any other P-N junction in said semiconductor body, forming isolation moats in said body extending inwardly from said second surface so that said region of P conductivity tyoe is encompassed by one of said moats, forming a layer of insulating material on said second surface and in said moats, providing a support body on said layer of insulating material, and removing a portion of said semiconductor body on the side of said first surface until a new surface is provided through which the layer of insulating material in said moat extends and through which the regions of N and P conductivity sypes extend to provide an island of N-type semiconductor material and an island of P-typ semiconductor material which are dielectrically isolated from each other and from the support body.

Claim 3

A method as in claim 1 together with the step of fabricating complementary NPN and PNP devices with compatible voltage ratings in said islands of N and P conductivity types.

Claim 4

A method as in claim 1 together with the step of forming a heavily doped region of N conductivity type in said region of N conductivity type extending inwardlY from said second surface and wherein the moats are positioned so that one of the moats encompasses the region of N conductivity type with the heavily doped region therein to provide an island with the heavily doped region at the bottom of the island and spaced below the new surface.

Claim 5

A method as in claim 1 wherein said island of N conductivity type serves as a first region of N conductivity type and wherein said island of P conductivity type serves as a second region of P conductivity type together with he steps in the order named of forming a third region of P conductivity type in said first region, forming a fourth region of N conductivity type in said second region, forming a fifth region of N conductivity type in said third region, forming a sixth region of P conductivity tpe in said fourth region, forming a layer of insulating material on said new surface over said islands and providing electrical contact elements on said last named layer of nsulating material and extending through said last named layer of insulating material for making contact to said first, third and fifth regions and to said second, fourth and sixth regions whereby the first, third and fifth regions serve as the collector, base and emitter of an NPN transistor and the second, fourth and sixth regions serve as the collector, base and emitter f a PNP transistor.

Claim 6

A method as in claim 1 wherein said island of N conductivity type serves as a first region of N conductivity type and wherein said island of P conductivity type serves as a second region of P conductivity type together with the steps in the order named of forming a third region of N conductivity type in said second region, forming a fourth region of P conductivity type in said first region, forming a fifth region of P conductivity type in said third region, forming a sixth region of N conductivity type in said fourth region, forming a layer of insulating material on sadi new surface over said island of N conductivity type and said island of P conductivity type and providing electrical contact elements on said last named layer of insulating material and extending through said last named layer of insulating material for making contact to said first, fourth and sixth regions and said second, third and fifth regions, whereby the first, fourth and sixth regions serve as a collector, base and emitter of the NPN transistor and the second, third and fifth regions serve as a collector, base and emitter of the PNP transistor.

Claim 7

In a method for making complementary NPN and PNP transistors having compatible voltage ratings in a semiconductor body having front and back surfaces and having N-type conductivity, fiffusing an impurity of P-type conductivity through the back surface of the semiconductor body to provide a deep diffused P-type region of P-type conductivity in said semiconductor body to a depth ranging from 15 to 80 microns by diffusing a P-type impurity into said semiconductor body for a periof of time ranging from 8 hours to 100 hours at a temperature ranging from 1,200* to 1,300* C to provide a P-N junction extending to said second surface, said step of forming the deep diffused region being performed prior to the formation of any other P-N junction in said semiconductor body, forming isolation moats in said semiconductor body extending inwardly from said back surface so that said P-type region is encompassed by one of said moats, forming a layer of insulating material on said back surface and extending into said moats, removing a portion of the semiconductor body from the front surface so that a new surface is provided through which said layer of insulating material extends and to expose the back side of said region of P-type conductivity and to expose an N-type region, fabricating an NPN transistor in said N-type region of said semiconductor body by introducing impurities through said new surface, and fabriCating a PNP transistor of a complementary type in the P-type region of opposite conductivity by introducing impurities through said new surface to provide a PNP transistor complementary to the NPN transistor in the semiconductor body.

Claim 8

In a method for making complementary NPN and PNP transistors having compatible voltage ratings in a semiconductor body having front and back surfaces and having N-type conductivity, fiffusing an impurity of P-type conductivity through the back surface of the semiconductor body to provide a deep diffused P-type region of P-type conductivity in said semiconductor body to a depth ranging from 15 to 80 microns by diffusing a P-type impurity into said semiconductor body for a periof of time ranging from 8 hours to 100 hours at a temperature ranging from 1,200* to 1,300* C to provide a P-N junction extending to said second surface, said step of forming the deep diffused region being performed prior to the formation of any other P-N junction in said semiconductor body, forming isolation moats in said semiconductor body extending inwardly from said back surface so that said P-type region is encompassed by one of said moats, forming a layer of insulating material on said back surface and extending into said moats, removing a portion of the semiconductor body from the front surface so that a new surface is provided through which said layer of insulating material extends and to expose the back side of said region of P-type conductivity and to expose an N-type region, fabricating an NPN transistor in said N-type region of said semiconductor body by introducing impurities through said new surface, and fabriCating a PNP transistor of a complementary type in the P-type region of opposite conductivity by introducing impurities through said new surface to provide a PNP transistor complementary to the NPN transistor in the semiconductor body.

Claim 9

A method as in claim 6 wherein said P-type region has an impurity concentration which increases with depth from the new surface, together with the step of diffusing an N-type impurity into said semiconductor body through said back surface to provide a heavily doped N-type region which forms a buried layer for the NPN transistor.

Claim 10

A method as in claim 6 wherein the diffusion through the back surface is carried out to a depth of approximately 60 microns.