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US4293587A Expired / Lapsed US ⏱️ 0.0 years remaining

Low resistance backside preparation for semiconductor integrated circuit chips

Assignee: Zilog Inc
•
Filing: 1978-11-09
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Granted: 1981-10-06
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Expires: 1998-11-09
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Abstract

Abstract To provide an electrically conductive p-type wafer backside for semiconductor integrated circuit chips (die), a process is provided consisting of applying a thin layer of aluminum on a silicon dioxide free surface of the chip, followed by a layer of gold, then alloying the metals to diffuse the gold and traces of aluminum into the chip surface. The surface thus prepared can then be advantageously die attachable to a receiving surface by either eutectic alloy or conductive polymer techniques.

Inventors

  • 👤 Richard K. Trueblood

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:01
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/50; H10W; H10W72/00; H10W72/30; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/033; Y10S438/00; Y10S438/906; Y10S438/974

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 113 words
A process for preparing the surface of a semiconductor integrated circuit chip for conductive attachment to a receiving surface comprising removing substantially all surface contaminants and silicon dioxide from a surface of said chip, applying a layer of aluminum to said surface, applying a layer of gold to said aluminum layer, having a thickness in the range of twenty to forty times thicker than said aluminum layer, and alloying said aluminum and gold layers at a temperature range between 380° and 440° C. for a time of four to six minutes in a nitrogen atmosphere, whereby gold is driven through said aluminum layer to penetrate said silicon surface, pulling traces of aluminum therewith.
Claim 2
Dependent Claim 113 words
A process for preparing the surface of a semiconductor integrated circuit chip for conductive attachment to a receiving surface comprising removing substantially all surface contaminants and silicon dioxide from a surface of said chip, applying a layer of aluminum to said surface, applying a layer of gold to said aluminum layer, having a thickness in the range of twenty to forty times thicker than said aluminum layer, and alloying said aluminum and gold layers at a temperature range between 380° and 440° C. for a time of four to six minutes in a nitrogen atmosphere, whereby gold is driven through said aluminum layer to penetrate said silicon surface, pulling traces of aluminum therewith.
Claim 3
Dependent Claim 19 words
The process of claim 1 further comprising the step of contacting a conductive polymer to the alloyed gold layer.
Claim 4
Dependent Claim 17 words
The process of claim 1 wherein the metal layers are applied by sputtering, evaporation, and/or vapor deposition.
Claim 5
Dependent Claim 20 words
The process of claim 1 wherein said aluminum layer has a thickness in the range of 50 to 150 A.
Claim 6
Dependent Claim 23 words
The process of claim 1 wherein the method of removing surface contaminants is selected from the group consisting of sandblasting, grinding and etching.

References Cited (Backward Citations)

JPS4813265B1 Cited
US3942244A Cited
US3650826A Cited
US3665594A Cited
US3544704A Cited
US3729807A Cited
US3702787A Cited
US4023725A Cited
US4012832A Cited
US4181249A Cited
JPS54152967A Cited
US4233103A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-10-05 1985-04-06 1985-10-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-10-05 1989-04-06 1989-10-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-10-05 1993-04-06 1993-10-06 $7700.00 Window Closed / Lapsed

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