Semiconductor device

Claim 2

A semiconductor device for use in bootstrap circuits, comprising: a semiconductor substrate, having a surface, of a first conductivity type; first, second and third regions of a second conductivity type formed in said semiconductor substrate; a first insulating layer having a first portion with a surface formed on the surface of said semiconductor substrate between said first and second regions, said first insulating layer further having a second portion with a surface formed on the surface of said semiconductor substrate adjacent to said third region; a first electrically conductive layer formed on the surface of said first portion of said first insulating layer, said first electrically conductive layer, said first portion of said first insulating layer and said first and second regions forming an MIS transistor; a second electrically conductive layer, having a surface, formed on the surface of said second portion of said first insulating layer, wherein a capacitor is formed by said surface of said second electrically conductive layer and by the surface of said substrate adjacent to said third region, said surface of said second electrically conductive layer and said surface of said substrate separated by said second portion of said first insulating layer, said second electrically conductive layer electrically connected to said second region; and a substantially radiation opaque layer, having a first contact formed on said second region and having a second contact formed on said second electrically conductive layer, for preventing radiation from penetrating into said second region, said substantially radiation opaque layer overlying the whole of said second region.

Claim 3

A semiconductor device for use in bootstrap circuits comprising: a semiconductor substrate, having a surface, of a first conductivity type; first, second and third regions of a second conductivity type formed in said semiconductor substrate; a first insulating layer having a first portion with a surface formed on the surface of said substrate between said first and second regions, said first insulating layer further having a second portion with a surface formed on the surface of said substrate adjacent to said third region; a second insulating layer formed on the surface of said substrate between said second region and said second portion of said first insulating layer; a first electrically conductive layer formed on the surface of said first portion of said first insulating layer, said first electrically conductive layer, said first portion of said first insulating layer and said first and second regions forming an MIS transistor; a second electrically conductive layer, having a surface, formed on the surface of said second portion of said first insulating layer and extending to said second insulating layer, wherein a capacitor is formed by said surface of said second electrically conductive layer and said surface of said semiconductor substrate adjacent to said third region, said surface of said second electrically conductive layer and said surface of said semiconductor substrate separated by said second portion of said first insulating layer; a third electrically conductive layer for connecting said second region and said second electrically conductive layer, said third electrically conductive layer overlying the whole of said second region; and a third insulating layer formed between said first and second electrically conductive layers, and said third electrically conductive layer.

Claim 4

A semiconductor device for use in bootstrap circuits comprising: a semiconductor substrate, having a surface, of a first conductivity type; first, second and third regions of a second conductivity type formed in said semiconductor substrate; a first insulating layer having a first portion with a surface formed on the surface of said substrate between said first and second regions, said first insulating layer further having a second portion with a surface formed on the surface of said substrate adjacent to said third region; a second insulating layer formed on the surface of said substrate between said second region and said second portion of said first insulating layer; a first electrically conductive layer formed on the surface of said first portion of said first insulating layer, said first electrically conductive layer, said first portion of said first insulating layer and said first and second regions forming an MIS transistor; a second electrically conductive layer, having a surface, formed on the surface of said second portion of said first insulating layer and extending to said second insulating layer, wherein a capacitor is formed by said surface of said second electrically conductive layer and said surface of said semiconductor substrate adjacent to said third region, said surface of said second electrically conductive layer and said surface of said semiconductor substrate separated by said second portion of said first insulating layer; a third electrically conductive layer for connecting said second region and said second electrically conductive layer, said third electrically conductive layer overlying the whole of said second region; and a third insulating layer formed between said first and second electrically conductive layers, and said third electrically conductive layer.

Claim 5

A device as set forth in claim 2, wherein said third electrically conductive layer is connected to said second insulating layer at a contact, said contact formed adjacent to said second region.

Claim 6

A device as set forth in claim 2, wherein said first insulating layer has a third portion adjacent to said second region, said device further comprising a fourth electrically conductive layer formed on said third portion of said first insulating layer, said third electrically conductive layer connected to said fourth electrically conductive layer.

Claim 7

A device as set forth in claim 2, further comprising a fifth electrically conductive layer formed on said second insulating layer adjacent to said second region.

Claim 8

A device as set forth in claim 1 or 2, wherein said semiconductor substrate is silicon.

Claim 9

A device as set forth in claim 2, 3, 4 or 5 wherein said first, second and third insulating layers are silicon dioxide.

Claim 10

A device as set forth in claim 2, 3, 4 or 5 wherein said first insulating layer is a silicon dioxide layer having a thickness of from 800 to 1,000 angstrom units.

Claim 11

A device as set forth in claim 2, 3, 4 or 5 wherein said second insulating layer is a silicon dioxide layer having a thickness greater than 1,000 angstrom units.

Claim 12

A device as set forth in claim 1 or 2, wherein said first and second electrically conductive layers are polycrystalline silicon layers.

Claim 13

A device as set forth in claim 1 or 2, wherein said first and second electrically conductive layers are molybdenum layers.

Claim 14

A device as set forth in claim 1 or 2, wherein said first and second electrically conductive layers are tungsten layers.

Claim 15

A device as set forth in claim 2, wherein said third electrically conductive layer is an aluminum layer.

Claim 16

A semiconductor device, for use in an erasable and programmable read-only memory device, comprising: means for providing first and second input signals; a power supply line; a ground line; a first MIS field effect transistor, having a gate and a source operatively connected to said power supply line, and having a drain; a second MIS field effect transistor, having a source operatively connected to the drain of said first MIS field effect transistor at a first node, having a gate operatively connected to receive said first input signal, and having a drain operatively connected to said ground line; a third MIS field effect transistor, having a gate operatively connected to said power supply line, having a drain operatively connected at said first node, and having a source; a fourth MIS field effect transistor, having a source operatively connected to said power supply line, having a gate operatively connected to the source of said third MIS field effect transistor at a second node, and having a drain; a fifth MIS field effect transistor, having a source operatively connected to the drain of said fourth MIS field effect transistor at a third node, having a gate operatively connected to receive said second input signal, and having a drain operatively connected to the ground line; a capacitor operatively connected between said second and third nodes; and cover means for protecting the source p-n junction of said third MIS field effect transistor by preventing radiation from penetrating thereinto when the erasable and programmable read-only memory device is irradiated.

Claim 17

A semiconductor device, for use in an erasable and programmable read-only memory device, comprising: means for providing first and second input signals; a power supply line; a ground line; a first MIS field effect transistor, having a gate and a source operatively connected to said power supply line, and having a drain; a second MIS field effect transistor, having a source operatively connected to the drain of said first MIS field effect transistor at a first node, having a gate operatively connected to receive said first input signal, and having a drain operatively connected to said ground line; a third MIS field effect transistor, having a gate operatively connected to said power supply line, having a drain operatively connected at said first node, and having a source; a fourth MIS field effect transistor, having a source operatively connected to said power supply line, having a gate operatively connected to the source of said third MIS field effect transistor at a second node, and having a drain; a fifth MIS field effect transistor, having a source operatively connected to the drain of said fourth MIS field effect transistor at a third node, having a gate operatively connected to receive said second input signal, and having a drain operatively connected to the ground line; a capacitor operatively connected between said second and third nodes; and cover means for protecting the source p-n junction of said third MIS field effect transistor by preventing radiation from penetrating thereinto when the erasable and programmable read-only memory device is irradiated.

Claim 18

A device as set forth in claim 14, wherein said MIS field effect transistors are MOS field effect transistors.