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US4288872A
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Equalizer for the correction of digital signals
Assignee: Telecom Italia SpA
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Filing: 1980-05-09
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Granted: 1981-09-08
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Expires: 2000-05-09
Abstract
Abstract An equalizer designed to correct both precursor and postcursor distortion in signal samples periodically obtained from a digital signal train comprises two parallel, mutually complementary circuit branches each including an upstream filter for linearly correcting one type of distortion and a downstream cell for nonlinearly compensating the other type of distortion. The compensating cell of the first branch includes an adder algebraically combining a feed-forward signal with a signal at least partly freed from postcursor interference in the corresponding upstream filter; the second branch includes another adder algebraically combining a feedback signal from its compensating cell with a prefiltered signal at least partly freed from precursor interference. Purged signals from both adders are combined in a summing stage followed by a decision unit which emits a quantized pulse to be used either directly as a decided symbol or as a source of corrective pulses for postcursor and precursor elimination in another linearly prefiltered sample.
Inventors
- 👤 Giovanni Tamburelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:10
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133; H04L25/03019; H04L25/03025
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
354 words
An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch connected to said receiving means, said first branch including first filter means for converting a given signal sample into a first linearly prefiltered signal with at least partial suppression of postcursor effects, first threshold means connected to said first filter means for deriving a first quantized pulse from said first prefiltered signal, second filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse, first delay means connected to said first filter means for emitting a retarded signal corresponding to said first prefiltered signal, and first adding means connected to said first delay means and to said second filter means for algebraically combining said retarded signal with said precursor-compensating signal to produce a first purged signal; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including third filter means for converting said given signal sample into a second linearly prefiltered signal with at least partial suppression of precursor effects, second threshold means in a feedback loop with an input end downstream of said third filter means for deriving a second quantized pulse from said second prefiltered signal, fourth filter means in said feedback loop connected to said second threshold means for generating a postcursor-compensating signal from said second quantized pulse, second adding means upstream of said input end connected to said third and fourth filter means for algebraically combining said second prefiltered signal with said postcursor-compensating signal to produce a corrected feedback signal, and second delay means connected to said second adding means downstream of said input end for emitting a second purged signal temporally correlated with said first purged signal; summing means connected to said first and second branches for algebraically combining said first and second purged signals into a resulting signal; and decision means connected to said summing means for converting said resulting signal into a quantized output pulse.
Claim 2
Dependent Claim
354 words
An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch connected to said receiving means, said first branch including first filter means for converting a given signal sample into a first linearly prefiltered signal with at least partial suppression of postcursor effects, first threshold means connected to said first filter means for deriving a first quantized pulse from said first prefiltered signal, second filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse, first delay means connected to said first filter means for emitting a retarded signal corresponding to said first prefiltered signal, and first adding means connected to said first delay means and to said second filter means for algebraically combining said retarded signal with said precursor-compensating signal to produce a first purged signal; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including third filter means for converting said given signal sample into a second linearly prefiltered signal with at least partial suppression of precursor effects, second threshold means in a feedback loop with an input end downstream of said third filter means for deriving a second quantized pulse from said second prefiltered signal, fourth filter means in said feedback loop connected to said second threshold means for generating a postcursor-compensating signal from said second quantized pulse, second adding means upstream of said input end connected to said third and fourth filter means for algebraically combining said second prefiltered signal with said postcursor-compensating signal to produce a corrected feedback signal, and second delay means connected to said second adding means downstream of said input end for emitting a second purged signal temporally correlated with said first purged signal; summing means connected to said first and second branches for algebraically combining said first and second purged signals into a resulting signal; and decision means connected to said summing means for converting said resulting signal into a quantized output pulse.
Claim 3
Dependent Claim
21 words
An equalizer as defined in claim 1, further comprising a shaping filter inserted between said summing means and said decision means.
Claim 4
Dependent Claim
88 words
An equalizer as defined in claim 1 or 2, further comprising pulse-generating means connected to said decision means for deriving at least one corrective signal from said output pulse, circuit means connected to said receiving means in parallel with said first and second branches, algebraic means connected to said pulse-generating means and to said circuit means for superimposing said corrective signal upon a signal sample adjacent said given sample to produce a compensated signal, and other decision means connected to said algebraic means for quantizing said compensated signal.
Claim 5
Dependent Claim
170 words
An equalizer as defined in claim 3 wherein said pulse-generating means comprises fifth and sixth filter means connected in parallel for concurrently emitting a pair of corrective signals; said circuit means including a third and a fourth circuit branch respectively provided with seventh filter means for at least partially suppressing postcursor effects in said adjacent sample and eighth filter means for at least partially suppressing precursor effects in said adjacent sample; said algebraic means including third adding means in said third branch connected to said fifth filter means for receiving one of said corrective signals to produce a third purged signal, fourth adding means in said fourth branch connected to said sixth filter means for receiving the other of said corrective signals to produce a fourth purged signal, and additional summing means connected to said third and fourth adding means to combine said third and fourth purged signals into said compensated signal; said circuit means further including supplemental delay means for temporally correlating said corrective signals with said adjacent sample.
Claim 6
Dependent Claim
28 words
An equalizer as defined in claim 4 wherein said supplemental delay means comprises a common delay line inserted between said receiving means and said third and fourth branches.
Claim 7
Dependent Claim
55 words
An equalizer as defined in claim 5 wherein said supplemental delay means further comprises two additional delay lines, one of said additional delay lines being inserted between said common delay line and said seventh filter means, the other of said additional delay lines being inserted between said fourth adding means and said additional summing means.
Claim 8
Dependent Claim
29 words
An equalizer as defined in claim 5 wherein said supplemental delay means further comprises an additional delay line inserted between said sixth filter means and said fourth adding means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-07 | 1985-03-09 | 1985-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-07 | 1989-03-09 | 1989-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-07 | 1993-03-09 | 1993-09-08 | $7700.00 | Window Closed / Lapsed |