Junction type field effect transistor with source at oxide-gate interface depth to maximize μ

Claim 2

A junction type field effect transistor comprising: a drain region formed of a semiconductor layer of one conductivity type; a source region constituted by a first layer of said one conductivity type which is formed to a prescribed depth from the surface of the semiconductor layer at a high concentration of impurity; an insulation layer formed in the semiconductor layer closely around the source region, with said source region being sufficiently deep with respect to said insulation layer, at least from the surface of said semiconductor layer, to establish triode voltage-current characteristics, and said source region being formed sufficiently shallow with respect to said insulation layer, at least from the surface of said semiconductor layer, to maximize voltage-amplifying degree μ; and a gate region constituted by a second layer of the opposite conductivity type to the semiconductor layer which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to extend from the proximity of the source region away from the source region.

Claim 3

The junction type field effect transistor according to claim 1, wherein the gate region surrounds the source region.

Claim 4

The junction type field effect transistor according to claim 2, wherein the distance between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of the distance between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.

Claim 5

The junction type field effect transistor according to claim 1, wherein the impurity concentration of the source region ranges from 5×10 19 to 3×10 20 atoms/cm 3 .

Claim 6

The junction type field effect transistor according to claim 1, wherein the impurity concentration of the gate region ranges from 1×10 19 to 5×10 19 atoms/cm 3 .

Claim 7

The junction type field effect transistor according to claim 1, wherein the impurity concentration of the semiconductor layer ranges between 1×10 14 and 1×10 15 atoms/cm 3 .

Claim 8

The junction type field effect transistor according to claim 1, wherein the source region has a depth of 5,000 to 7,000 A.

Claim 9

A junction type field effect transistor comprising: a drain region formed of an N-type semiconductor layer having an impurity concentration of 1×10 14 to 1×10 15 atoms/cm 3 ; a source region constituted by an N-type layer formed to a depth of 5,000 to 7,000 A from the surface of the semiconductor layer at an impurity concentration of 5×10 19 to 3×10 20 atoms/cm 3 ; an insulation layer surrounding the source region and formed in the semiconductor layer closely around the source region, with said source region being sufficiently deep with respect to said insulation layer, at least from the surface of the semiconductor layer, to establish triode voltage-current characteristics and said source region being formed sufficiently shallow with respect to said insulation layer, at least from the surface of the semiconductor layer, to maximize voltage-amplifying degree μ; and a gate region constituted by a P-type layer having an impurity concentration of 1×10 19 to 5×10 19 atoms/cm 3 which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to be laterally displaced from said source region at least 1.3 microns and extending away from the source region to surround that portion of the semiconductor layer in which the source region is formed, and wherein a distance l between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of a distance d between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.

Claim 10

A junction type field effect transistor comprising: a drain region formed of an N-type semiconductor layer having an impurity concentration of 1×10 14 to 1×10 15 atoms/cm 3 ; a source region constituted by an N-type layer formed to a depth of 5,000 to 7,000 A from the surface of the semiconductor layer at an impurity concentration of 5×10 19 to 3×10 20 atoms/cm 3 ; an insulation layer surrounding the source region and formed in the semiconductor layer closely around the source region, with said source region being sufficiently deep with respect to said insulation layer, at least from the surface of the semiconductor layer, to establish triode voltage-current characteristics and said source region being formed sufficiently shallow with respect to said insulation layer, at least from the surface of the semiconductor layer, to maximize voltage-amplifying degree μ; and a gate region constituted by a P-type layer having an impurity concentration of 1×10 19 to 5×10 19 atoms/cm 3 which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to be laterally displaced from said source region at least 1.3 microns and extending away from the source region to surround that portion of the semiconductor layer in which the source region is formed, and wherein a distance l between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of a distance d between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.

Claim 11

The junction type field effect transistor according to claim 8, wherein the distance d is about 4 to 7 microns.

Claim 12

A junction type field effect transistor comprising: a drain region formed of an N-type semiconductor layer having an impurity concentration of 1×10 14 to 1×10 15 atoms/cm 3 ; a source region constituted by an N-type layer formed to a depth of 5,000 to 7,000 A from the surface of the semiconductor layer at an impurity concentration of 5×10 19 to 3×10 20 atoms/cm 3 ; an insulation layer surrounding the source region and formed in the semiconductor layer closely around the source region to the same depth as the source region at least from the surface of the semiconductor layer; and a gate region constituted by a P-type layer having an impurity concentration of 1×10 19 to 5×10 19 atoms/cm 3 which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to be laterally displaced from said source region at least 1.3 microns and extending away from the source region to surround that portion of the semiconductor layer in which the source region is formed and wherein a distance l between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of a distance d between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.

Claim 13

A junction type field effect transistor comprising: a drain region formed of an N-type semiconductor layer having an impurity concentration of 1×10 14 to 1×10 15 atoms/cm 3 ; a source region constituted by an N-type layer formed to a depth of 5,000 to 7,000 A from the surface of the semiconductor layer at an impurity concentration of 5×10 19 to 3×10 20 atoms/cm 3 ; an insulation layer surrounding the source region and formed in the semiconductor layer closely around the source region to the same depth as the source region at least from the surface of the semiconductor layer; and a gate region constituted by a P-type layer having an impurity concentration of 1×10 19 to 5×10 19 atoms/cm 3 which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to be laterally displaced from said source region at least 1.3 microns and extending away from the source region to surround that portion of the semiconductor layer in which the source region is formed and wherein a distance l between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of a distance d between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.

Claim 14

The junction type field effect transistor according to claim 10, wherein the distance d is about 4 to 7 microns.

Claim 15

The junction type field effect transistor according to claim 1 wherein said insulation layer formed in said semiconductor layer closely around the source region is formed in said semiconductor region to substantially the same depth as the source region at least from the surface of said semiconductor layer.

Claim 16

The junction type field effect transistor according to claim 8 wherein said insulation layer formed in said semiconductor layer closely around the source region is formed in said semiconductor region to substantially the same depth as the source region at least from the surface of said semiconductor layer.