US3977017A
Expired / Lapsed
US
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Multi-channel junction gated field effect transistor and method of making same
Assignee: Sony Corp
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Filing: 1975-01-20
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Granted: 1976-08-24
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Expires: 1995-01-20
Abstract
Abstract A multi-channel junction gated field effect transistor which gives good triode characteristics is formed on a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type. A mosaic shape semiconductor gate region of the opposite conductivity type is formed in the substrate below one major surface thereof, the mosaic shape of the gate region forming a plurality of windows filled with portions of the substrate which thus provide channels leading to the main body of the substrate, the main body of the substrate providing the drain region for the transistor. A corresponding relatively thick mosaic shape insulating layer overlies the mosaic shape gate region has a plurality of windows, which windows are smaller than the windows of the gate region and of the same configuration, the windows of the insulating layer being aligned with the windows of the gate region. The source consists of two regions, one which is heavily doped with impurity of the first conductivity type and the second which has less doping than that of the first source region but of greater doping than the drain region and the channel regions. The first source region is completely within the windows of the insulating layer, while the second source region is partially within such windows and extends down as a tongue partially into the channel. Electrodes are provided for the source, gate and drain regions. The substrate is preferably N-type silicon having a doping level of 10 14 to 10 15 atoms/cm 3 . The first source region preferably has a doping higher than 5 × 10 19 , while the second source region with its tongues has a doping level between 10 16 and 10 18 atoms/cm 3 . If the doping level of the second source region is 10 18 atoms/cm 3 , it is possible to have the substrate doped to 10 16 atoms/cm 3 .
Inventors
- 👤 Akiyasu Ishitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/202; Y; Y10; Y10S; Y10S148/00; Y10S148/088
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
234 words
A multi-channel junction gated field effect transistor comprising a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type, a mosaic shape semiconductor gate region of the opposite conductivity type formed in said substrate below one major surface thereof, the mosaic shape of said gate region forming a plurality of windows filled with portions of said substrate which provide channels for said field effect transistor, the main body portion of said substrate providing the drain for said field effect transistor, a corresponding relatively thick mosaic shape insulating layer overlying said mosaic shape gate region having a plurality of windows smaller than said windows of said gate region of the same configuration and aligned with said windows of said gate region, a first source region heavily doped with impurities the first impurity type completely within said windows of said insulating layer extending down from the outer surface of said insulating layer to a point short of the bottom of said windows of said insulating layer, a second source region extending down from at least one of said first source regions and being less heavily doped than said first source region but more heavily doped than said substrate and of said first impurity type doping, said second source region being partially within a window of said insulating layer and extending down below said window of said insulating layer partially into a channel.
Claim 2
Dependent Claim
234 words
A multi-channel junction gated field effect transistor comprising a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type, a mosaic shape semiconductor gate region of the opposite conductivity type formed in said substrate below one major surface thereof, the mosaic shape of said gate region forming a plurality of windows filled with portions of said substrate which provide channels for said field effect transistor, the main body portion of said substrate providing the drain for said field effect transistor, a corresponding relatively thick mosaic shape insulating layer overlying said mosaic shape gate region having a plurality of windows smaller than said windows of said gate region of the same configuration and aligned with said windows of said gate region, a first source region heavily doped with impurities the first impurity type completely within said windows of said insulating layer extending down from the outer surface of said insulating layer to a point short of the bottom of said windows of said insulating layer, a second source region extending down from at least one of said first source regions and being less heavily doped than said first source region but more heavily doped than said substrate and of said first impurity type doping, said second source region being partially within a window of said insulating layer and extending down below said window of said insulating layer partially into a channel.
Claim 3
Dependent Claim
21 words
A multi-channel junction gated field effect transistor according to claim 1, in which said source, channel and drain regions are silicon.
Claim 4
Dependent Claim
68 words
A multi-channel junction gated field effect transistor according to claim 1, in which said drain regions are N-type silicon having impurity doping of 10 14 to 10 15 atoms/cm 3 , said first source regions are N-type silicon having impurity doping of 5 × 10 19 atoms/cm 3 and said second source regions are N-type silicon having impurity doping of 10 16 to 10 18 atoms/cm 3 .
Claim 5
Dependent Claim
30 words
A multi-channel junction gated field effect transistor according to claim 1, in which said insulating layer is a three part sandwich composed of silicon dioxide, silicon nitride and silicon dioxide.
Claim 6
Dependent Claim
25 words
A multi-channel junction gated field effect transistor according to claim 1, in which said second source regions correspond in number to said first source regions.
Claim 7
Dependent Claim
28 words
A multi-channel junction gated field effect transistor according to claim 1, in which said second source regions extend down from less than half of the first source regions.
Claim 8
Dependent Claim
199 words
A junction gated field effect transistor having a plurality of channels, comprising: a. a drain region of a first conductivity type of semiconductor material common to said plurality of channels; b. a mesh-like gate region formed on said drain region of the second conductivity type, forming a rectifying P-N junction with said drain region and defining said plural channels, c. a plurality of first source regions of first conductivity type formed above said channels, d. a plurality of second source regions of the first conductivity type formed on and adjacent to at least a part of said channels, e. said first source regions having higher impurity conductivity than said second source regions, f. said second source regions having a higher impurity concentration than said channel regions and said drain region, g. conductive electrodes for said first source, gate and drain regions, and the lower surface of said first source regions lying in a plane above the plane of the upper ends of said gate region, the upper ends of said second source regions being interfaced with the lower ends of said first source regions, and the lower ends of said second source regions extending part way into said channels.
Claim 9
Dependent Claim
199 words
A junction gated field effect transistor having a plurality of channels, comprising: a. a drain region of a first conductivity type of semiconductor material common to said plurality of channels; b. a mesh-like gate region formed on said drain region of the second conductivity type, forming a rectifying P-N junction with said drain region and defining said plural channels, c. a plurality of first source regions of first conductivity type formed above said channels, d. a plurality of second source regions of the first conductivity type formed on and adjacent to at least a part of said channels, e. said first source regions having higher impurity conductivity than said second source regions, f. said second source regions having a higher impurity concentration than said channel regions and said drain region, g. conductive electrodes for said first source, gate and drain regions, and the lower surface of said first source regions lying in a plane above the plane of the upper ends of said gate region, the upper ends of said second source regions being interfaced with the lower ends of said first source regions, and the lower ends of said second source regions extending part way into said channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-24 | 1980-02-23 | 1980-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-24 | 1984-02-23 | 1984-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-24 | 1988-02-23 | 1988-08-24 | $7700.00 | Window Closed / Lapsed |