FET Containing stacked gates

Claim 2

A field effect transistor (FET) which comprises a floating gate, a control gate above said floating gate, insulator between said floating gate and control gate; said floating gate and said control gate being self-aligned in both the width and length dimensions with respect to each other; source and drain regions wherein the floating gate and control gate are self-aligned with respect to said source and drain regions.

Claim 3

The field effect transistor of claim 1 wherein said floating gate is selected from the group of polycrystalline silicon, refractory metal, and refractory metal silicide and said control gate is selected from the group of polycrystalline silicon and refractory metal silicide.

Claim 4

The field effect transistor of claim 1 wherein said floating gate is doped polycrystalline silicon and said control gate is doped polycrystalline silicon.

Claim 5

The field effect transistor (FET) of claim 1 which comprises: (a) semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (b) floating FET gate insulator over the channel region; (c) floating gate over said floating FET gate insulator; wherein the boundaries of said floating gate determine the boundaries of the channel region of the FET in the length dimension; (d) control gate stacked above said floating gate wherein the boundaries of said control gate also determine the boundaries of the channel region of the FET in the length dimension; said control gate being self-aligned with respect to said floating gate in both the length and width directions; (e) insulation between said floating gate and control gate; (f) doped source region of second and opposite conductive type; said source region being self-aligned with respect to one end of both of said FET floating gate and said control gate in the length direction; (g) doped drain region of a second and opposite conductive type; said drain region being self-aligned with respect to the other end of both of said floating gate and said control gate in the length direction; and (h) field oxide to isolate said FET from other like FETs and from other structures and circuits on the same semiconductive substrate.

Claim 6

The field effect transistor of claim 4 wherein said floating gate is selected from the group of polycrystalline silicon, refractory metal, and refractory metal silicide and said control gate is selected from the group of polycrystalline silicon and refractory metal silicide.

Claim 7

The field effect transistor of claim 5 wherein said refractory metal is selected from the group of tungsten, tantalum, hafnium, and rhodium.

Claim 8

The field effect transistor of claim 4 wherein said floating gate is doped polycrystalline silicon and said control gate is doped polycrystalline silicon.

Claim 9

The FET of claim 2 which further includes insulation layer at least over the FET source, and FET drain, a metallic-type high electrical conductivity interconnection line; electrical connection between the polycrystalline silicon control gate and said interconnection line; contact holes to provide vias for achieving electrical connection to FET source and drain regions; metallic-type high electrical conductivity interconnection lines making electrical connection to said FET source and drain regions through said vias; and electrical connections to said semiconductive substrate.

Claim 10

The field effect transistor of claim 3 wherein said semiconductive substrate is a p-type silicon substrate containing active p-type impurities.

Claim 11

The field effect transistor of claim 3 wherein said field oxide isolation is silicon dioxide.

Claim 12

The field effect transistor of claim 3 wherein said gate insulators are silicon dioxide.

Claim 13

The field effect transistor of claim 3 wherein said interconnection line is a metal.

Claim 14

The field effect transistor of claim 3 wherein said metal is aluminum.

Claim 15

The field effect transistor of claim 3 which further comprises contact holes to provide vias for achieving electrical connection to the semiconductive substrate.

Claim 16

The field effect transistor of claim 3 which further comprises electrical connection to the back surface of the semiconductive substrate.

Claim 17

An integrated circuit array containing a plurality of the FETs of claim 1.

Claim 18

An integrated circuit comprising an array of FETs prepared by the method which comprises: (a) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (b) providing and delineating predetermined insulating regions above or recessed into the substrate to provide isolating field regions between FETs of the array; (c) providing a first insulator for a floating gate to be subsequently defined; (d) depositing and doping a first layer of gate forming material above the first insulator; (e) providing a second and subsequent insulator above said first layer of gate forming material for a control gate to be subsequently delineated; (f) then depositing and doping a second and subsequent layer of gate forming material above said subsequent insulator; (g) delineating both the first layer of gate forming material and the subsequent layer or gate forming material employing the same lithographic mask to provide a floating gate and a control gate, respectively, which are self-aligned with each other in all lateral directions, and to provide etched regions which are to be subsequently doped for forming the source and drain regions; (h) thermally diffusing or ion implanting active impurities of a second type into predetermined regions of the semiconductive substrate beneath said etched regions to provide FET source and drain regions which are self-aligned with respect to said floating and control gates; (i) providing insulating layer; (j) delineating contact holes to source and drain regions; (k) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the control FET gates in the array of FETs and to FET sources and drains.

Claim 19

An integrated circuit comprising an array of FETs prepared by the method which comprises: (a) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (b) providing and delineating predetermined insulating regions above or recessed into the substrate to provide isolating field regions between FETs of the array; (c) providing a first insulator for a floating gate to be subsequently defined; (d) depositing and doping a first layer of gate forming material above the first insulator; (e) providing a second and subsequent insulator above said first layer of gate forming material for a control gate to be subsequently delineated; (f) then depositing and doping a second and subsequent layer of gate forming material above said subsequent insulator; (g) delineating both the first layer of gate forming material and the subsequent layer or gate forming material employing the same lithographic mask to provide a floating gate and a control gate, respectively, which are self-aligned with each other in all lateral directions, and to provide etched regions which are to be subsequently doped for forming the source and drain regions; (h) thermally diffusing or ion implanting active impurities of a second type into predetermined regions of the semiconductive substrate beneath said etched regions to provide FET source and drain regions which are self-aligned with respect to said floating and control gates; (i) providing insulating layer; (j) delineating contact holes to source and drain regions; (k) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the control FET gates in the array of FETs and to FET sources and drains.

Claim 20

The field effect transistor of claim 1 wherein both said floating and said control gates are polycrystalline silicon doped with the same type impurities.