Patent US4280271A successfully refreshed from Google Patents.
US4280271A
Expired / Lapsed
US
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Three level interconnect process for manufacture of integrated circuit devices
Assignee: Texas Instruments Inc
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Filing: 1979-10-11
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Granted: 1981-07-28
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Expires: 1999-10-11
Abstract
Abstract An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.
Inventors
- 👤 Perry W. Lou
- 👤 James E. Ponder
- 👤 Graham S. Tubbs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:34
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10P; H10P76/00; H10P76/40; H10W; H10W20/00; H10W20/01
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
183 words
A method of making an insulated gate field effect transistor and a cross-over connection in an integrated circuit comprising the steps of: (a) selectively growing thick field oxide using an oxidation mask to provide an enclosed surface area on said face for the transistor and a defined area for the cross-over connection, (b) introducing N-type impurity into said defined area to produce a conductive region and into the enclosed surface area to produce source and drain regions of an N-channel transistor leaving a space between said source and drain regions to create a channel, (c) depositing a layer of conductive material on said face over a thin gate insulator and patterning the conductive material to provide a gate of an N-channel transistor in said enclosed surface area in the space between the source and drain regions but leaving a gap between such gate and source and drain regions, the conductive material after patterning also extending across said conductive region, (d) and implanting N-type impurity into the enclosed surface area, self-aligned with said gate, adjacent said source and drain regions, to bridge said gaps.
Claim 2
Independent Claim
183 words
A method of making an insulated gate field effect transistor and a cross-over connection in an integrated circuit comprising the steps of: (a) selectively growing thick field oxide using an oxidation mask to provide an enclosed surface area on said face for the transistor and a defined area for the cross-over connection, (b) introducing N-type impurity into said defined area to produce a conductive region and into the enclosed surface area to produce source and drain regions of an N-channel transistor leaving a space between said source and drain regions to create a channel, (c) depositing a layer of conductive material on said face over a thin gate insulator and patterning the conductive material to provide a gate of an N-channel transistor in said enclosed surface area in the space between the source and drain regions but leaving a gap between such gate and source and drain regions, the conductive material after patterning also extending across said conductive region, (d) and implanting N-type impurity into the enclosed surface area, self-aligned with said gate, adjacent said source and drain regions, to bridge said gaps.
Claim 3
Dependent Claim
27 words
A method according to claim 1 wherein the step of patterning the layer of conductive material includes defining polycrystalline silicon interconnects which cross over N+ conductive regions.
Claim 4
Independent Claim
145 words
A method of making an insulated gate field effect transistor and cross-over connections in an integrated circuit comprising the steps of: (a) introducing impurity of one type into a first surface area of a face of a semiconductor body of opposite type to produce source and drain regions of a transistor and also into a second surface area of the face to produce a conductive region, (b) depositing a layer of conductive material on said face over a thin gate insulator and patterning the conductive material to provide a gate of the transistor on said first surface area spaced from the source and drain regions by gaps, and also to provide a conductor crossing over said second surface area, (c) and implanting said one type impurity into said first surface area, self-aligned with said gates, adjacent said source and drain regions, to bridge said gaps.
Claim 5
Independent Claim
145 words
A method of making an insulated gate field effect transistor and cross-over connections in an integrated circuit comprising the steps of: (a) introducing impurity of one type into a first surface area of a face of a semiconductor body of opposite type to produce source and drain regions of a transistor and also into a second surface area of the face to produce a conductive region, (b) depositing a layer of conductive material on said face over a thin gate insulator and patterning the conductive material to provide a gate of the transistor on said first surface area spaced from the source and drain regions by gaps, and also to provide a conductor crossing over said second surface area, (c) and implanting said one type impurity into said first surface area, self-aligned with said gates, adjacent said source and drain regions, to bridge said gaps.
Claim 6
Dependent Claim
31 words
A method according to claim 5 including the step of applying a second layer of conductive material over said face and patterning the second layer of conductive material to define interconnects.
References Cited (Backward Citations)
US3650019A
Cited
US3590471A
Cited
US3679492A
Cited
US3921282A
Cited
US3865650A
Cited
US3747200A
Cited
US4069067A
Cited
US4061506A
Cited
US4084311A
Cited
US4055444A
Cited
US4013489A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-27 | 1985-01-26 | 1985-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-27 | 1989-01-26 | 1989-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-27 | 1993-01-26 | 1993-07-28 | $7700.00 | Window Closed / Lapsed |