Multiple access store

Claim 2

A multiple access memory cell, comprising: flip-flop store means for operating in one switching state to store a binary one and for operating in another switching state to store a binary zero; at least one pair of accessing transistors, each transistor having means for operating in a conducting state to pass a sense current to read a switching state of said flip-flop store means and at least one of said accessing transistors having means for operating in a saturation state in response to a write signal to define a particular switching state for said flip-flop store means; mode select means for applying a write select voltage to said flip-flop store means to allow the flip-flop store means to change switching states in response to the saturation state of one of said accessing transistors and for applying a read select voltage to said flip-flop store means to prevent the flip-flop store means from changing switching states; and current supply means responsive to a word signal for supplying said sense current.

Claim 3

The multiple access memory cell of claim 1 wherein said flip-flop store means includes two NPN flip-flop transistors conductively connected at their emitters for receiving said write select voltage and said lower read select voltage, the base of each flip-flop transistor being conductively connected to the collector of the other flip-flop transistor, the base of one flip-flop transistor conductively connected to the base of one accessing transistor of said at least one pair of accessing transistors and the base of the other flip-flop transistor connected to the base of the other accessing transistor of said at least one pair of accessing transistors.

Claim 4

The multiple access memory cell of claim 1 wherein the emitters of said at least one pair of accessing transistors are conductively connected for receiving said sense current and said current supply means includes conducting means for receiving said word signal and a resistor for applying the word signal to the connected emitters of said accessing transistors.

Claim 5

The multiple access memory cell of claim 1 wherein the emitters of said at least one pair of accessing transistors are conductively connected for receiving said sense current and said current supply means includes a source transistor having a base for receiving said word signal and an emitter connected to a supply potential through a source resistor, said source transistor conducting in response to said word signal to supply said sense current to the connected emitters of the accessing transistors.

Claim 6

The multiple access memory cell of claim 1 including at least one pair of diodes, one diode of the pair connected to a collector of one accessing transistor of said at least one pair of accessing transistors and the other diode of the pair connected to a collector of the other accessing transistor, each of said diodes passing sense current when the connected accessing transistor is in said conducting state and each of said diodes being back biased in response to a write signal.

Claim 7

The apparatus of claim 5 including means for integrating said diodes into the structure of said accessing transistors, a cathode region of the diodes being common with a collector region of the transistors and an anode region of the diodes being a diffusion, implant or Schottky barrier.

Claim 8

The multiple access memory cell of claim 1 including a plurality of said pairs of accessing transistors, the accessing transistors of each pair having conductively connected emitters for receiving a sense current in response to a particular word signal, the base of one accessing transistor of each pair conductively connected to the base of one flip-flop transistor and the base of the other accessing transistor of each pair conductively connected to the base of the other flip-flop transistor.

Claim 9

The multiple access memory cell of claim 7 including a plurality of diodes, each diode connected to a collector of one of said accessing transistors for back biasing in response to a write signal applied to saturate the connected accessing transistor and for passing sense current when the connected accessing transistor is conducting.

Claim 10

The multiple access memory cell of claim 7 wherein at least one of said pairs of accessing transistors includes means for operating only to read the switching state of said flip-flop store means.

Claim 11

The multiple access memory cell of claim 1, wherein said mode select means applies the write select voltage to said flip-flop store means to maintain the flip-flop store means in a low power quiescent state.

Claim 12

In a memory apparatus of a type wherein a plurality of common-accessed memory cells are accessed for reading and writing over at least one pair of shared/bit/sense lines, the improvement of multiple access apparatus for writing a binary one or zero into at least one cell while concurrently reading the stored binary contents of at least one other cell during a memory access cycle, the multiple access apparatus comprising: a plurality of multiple access memory cells, each cell including, flip-flop store means for operating in one switching state to store a binary one and for operating in another switching state to store a binary zero; at least one pair of accessing transistors each transistor having means for operating in a conducting state to pass a sense current to read a switching state of said flip-flop store means and for operating in a saturation state in response to a write signal to define a particular switching state for said flip-flop store means; mode select means for applying a write select voltage to said flip-flop store means to allow the flip-flop store means to change switching states in response to the saturation state of one of said accessing transistors and for applying a read select voltage to said flip-flop store means to prevent the flip-flop store means from changing switching states; and current supply means connected to said at least one pair of accessing transistors for supplying said sense current to the at least one pair of accessing transistors in response to a particular word signal; means for connecting one bit/sense line of a bit/sense line pair for receiving sense current from one accessing transistor of an accessing transistor pair of each cell and for passing a particular write signal to the one accessing transistor of each accessing transistor pair, and for connecting the other bit/sense line of a bit/sense line pair for receiving sense current from the other accessing transistor of an accessing transistor pair of each cell and for passing another particular write signal to the other accessing transistor of each accessing transistor pair; word driver means for selectively applying a word signal to the current supply means of each pair of accessing transistors of the common-accessed memory cells; and mode driver means for selectively applying the read select voltage and the write select voltage to the mode select means of each of the common-accessed memory cells.

Claim 13

In a memory apparatus of a type wherein a plurality of common-accessed memory cells are accessed for reading and writing over at least one pair of shared/bit/sense lines, the improvement of multiple access apparatus for writing a binary one or zero into at least one cell while concurrently reading the stored binary contents of at least one other cell during a memory access cycle, the multiple access apparatus comprising: a plurality of multiple access memory cells, each cell including, flip-flop store means for operating in one switching state to store a binary one and for operating in another switching state to store a binary zero; at least one pair of accessing transistors each transistor having means for operating in a conducting state to pass a sense current to read a switching state of said flip-flop store means and for operating in a saturation state in response to a write signal to define a particular switching state for said flip-flop store means; mode select means for applying a write select voltage to said flip-flop store means to allow the flip-flop store means to change switching states in response to the saturation state of one of said accessing transistors and for applying a read select voltage to said flip-flop store means to prevent the flip-flop store means from changing switching states; and current supply means connected to said at least one pair of accessing transistors for supplying said sense current to the at least one pair of accessing transistors in response to a particular word signal; means for connecting one bit/sense line of a bit/sense line pair for receiving sense current from one accessing transistor of an accessing transistor pair of each cell and for passing a particular write signal to the one accessing transistor of each accessing transistor pair, and for connecting the other bit/sense line of a bit/sense line pair for receiving sense current from the other accessing transistor of an accessing transistor pair of each cell and for passing another particular write signal to the other accessing transistor of each accessing transistor pair; word driver means for selectively applying a word signal to the current supply means of each pair of accessing transistors of the common-accessed memory cells; and mode driver means for selectively applying the read select voltage and the write select voltage to the mode select means of each of the common-accessed memory cells.

Claim 14

The multiple access apparatus of claim 11, including, write latch means for storing a binary bit; writing means for applying a write signal on a bit/sense line to operate an accessing transistor of a common-accessed memory cell in the saturation state for storing a binary bit in the flip-flop store means of the cell, the bit stored in the cell corresponding to the bit stored in said write latch means, and sensing means for monitoring the sense current on each bit/sense line of a bit/sense line pair and for generating a logic signal for each bit/sense line, the logic signal for each line indicating the presence or absence of sense current on the line with respect to a zero reference current.

Claim 15

The apparatus of claim 12 wherein said sensing means includes means for compensating for a write signal on a bit/sense line to monitor the sense current on the line.

Claim 16

The apparatus of claim 12 wherein said sensing means includes means for exhibiting a low input impedance to said sense current.

Claim 17

The apparatus of claim 12 including logic means responsive to the bit stored in said write latch means and the logic signals generated for a particular bit/sense line pair by said sensing lach means, for generating a signal corresponding to the switching state of the flip-flop store means of a common-accessed memory cell being accessed by a read select voltage and a word signal defining the particular bit/sense line pair.

Claim 18

The multiple access apparatus of claim 11 including a plurality of pairs of accessing transistors and a plurality of bit/sense lines for accessing said common-accessed memory cells, each pair of bit/sense lines being connected to an associated pair of accessing transistors in each common-accessed memory cell and each pair of accessing transistors having a connected current supply means for supplying sense current in response to a particular word signal.

Claim 19

The apparatus of claim 11 wherein said means for connecting includes one diode connected between a collector of said one accessing transistor and said one bit/sense line and another diode connected between a collector of said other accessing transistor and said other bit/sense line.

Claim 20

The apparatus of claim 11 including at least one pair of read-only accessing transistors for each common-accessed memory cell and a read-only sense line connected to a particular transistor of each pair, each particular connected read-only accessing transistor of a cell operable in response to an applied read select voltage for the cell and word signal for the read-only accessing transistors of the cell to pass a sense current to the connected bit-sense line to register the switching state of the flip-flop store means of the cell.

Claim 21

The apparatus of claim 11 wherein said plurality of common accessed memory cells comprise a single column in a memory array, the array having a plurality of columns of memory cells, the mode select means of each cell in a row of cells being conductively connected to allow a mode selection for the entire row of cells and the current supply means for corresponding accessing transistor pairs of each cell in a row of cells conductively connected to receive a particular word signal to supply sense current to the corresponding accessing transistor pairs of each cell.

Claim 22

The apparatus of claim 11 wherein said mode driver means applies the write select voltage to the cells to maintain the cells in a low power quiescent state when no cell is being accessed and when at least one cell is being accessed said mode driver means applies the read select voltage to all cells not being written.

Claim 23

A multiple access memory array, comprising: a plurality of memory cells, each cell for storing a binary bit, the cells arranged in rows corresponding to binary words and the rows of cells arranged in a columnar relation to form columns of cells, the cells in each column accessed for read and write operations by at least one pair of bit/sense lines; a mode select line for each row of cells of the memory array, the mode select line of each row applying a mode select voltage to each cell of the row to define an accessing operation, one level of the mode select voltage defining a write operation for the cells of the row and another level of mode select voltage defining a read operation for the cells of a row; and at least one word select line for each row of cells of the memory array, each cell of a row of cells having, a memory flip-flop for storing a binary bit, source means for passing a sense current in response to a word signal applied on said at least one word select line, and accessing means for applying said sense current to access said memory flip-flop.

Claim 24

A multiple access memory array, comprising: a plurality of memory cells, each cell for storing a binary bit, the cells arranged in rows corresponding to binary words and the rows of cells arranged in a columnar relation to form columns of cells, the cells in each column accessed for read and write operations by at least one pair of bit/sense lines; a mode select line for each row of cells of the memory array, the mode select line of each row applying a mode select voltage to each cell of the row to define an accessing operation, one level of the mode select voltage defining a write operation for the cells of the row and another level of mode select voltage defining a read operation for the cells of a row; and at least one word select line for each row of cells of the memory array, each cell of a row of cells having, a memory flip-flop for storing a binary bit, source means for passing a sense current in response to a word signal applied on said at least one word select line, and accessing means for applying said sense current to access said memory flip-flop.

Claim 25

The multiple access memory array of claim 21 wherein each cell is accessed by a number n of pairs of bit/sense lines and each row of cells has n corresponding word select lines, each word select line of a row of cells applying a word signal to each cell of the row for accessing the memory flip-flop of the cell over a corresponding pair of bit/sense lines of the cell.

Claim 26

The multiple access memory array of claim 21 wherein said memory cells, mode select lines and word select lines are formed as a monolithic integrated circuit.

Claim 27

The multiple access memory array of claim 21 including means for defining an access cycle time for accessing cells of the array and means for operating the word select lines and the mode select lines of the array to execute a read operation for a cell and a write operation for a different cell concurrently during said access cycle time for each pair of bit/sense lines of the array.