US4259730A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IIL With partially spaced collars
Assignee: GKN Technology Ltd
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Filing: 1979-04-05
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Granted: 1981-03-31
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Expires: 1999-04-05
Abstract
Abstract The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I 2 L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I 2 L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I 2 L structures each which are cross-coupled in the manner of a flip-flop.
Inventors
- 👤 Klaus Heuber
- 👤 Erich Klink
- 👤 Volker Rudolph
- 👤 Siegfried K. Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H10; H10D; H10D84/00; H10D84/60; H10D84/63; H10D84/65; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
171 words
A monolithically integrated semiconductor structure comprising: a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type disposed on said semiconductor substrate, a separating zone defining a portion of said semiconductor layer having a given width between first and second sides thereof, said separating zone including a ring of heavily doped semiconductor material of said second conductivity type, an inverting transistor disposed within said separating zone, said transistor including a base zone of said first conductivity type and a collector zone of said second conductivity type disposed within said base zone, and an injection zone of said first conductivity type disposed within said separating zone and spaced from the base zone of said transistor by a given distance, the edge of said base zone and the edge of said injection zone facing each other extending from said first side to said second side, substantially the remaining edges of said base zone and of said injection zone being spaced from said separating zone by a predetermined distance.
Claim 2
Dependent Claim
171 words
A monolithically integrated semiconductor structure comprising: a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type disposed on said semiconductor substrate, a separating zone defining a portion of said semiconductor layer having a given width between first and second sides thereof, said separating zone including a ring of heavily doped semiconductor material of said second conductivity type, an inverting transistor disposed within said separating zone, said transistor including a base zone of said first conductivity type and a collector zone of said second conductivity type disposed within said base zone, and an injection zone of said first conductivity type disposed within said separating zone and spaced from the base zone of said transistor by a given distance, the edge of said base zone and the edge of said injection zone facing each other extending from said first side to said second side, substantially the remaining edges of said base zone and of said injection zone being spaced from said separating zone by a predetermined distance.
Claim 3
Dependent Claim
35 words
A monolithically integrated semiconductor structure as set forth in claim 1 further including an isolation zone made of semiconductor material of said first conductivity type surrounding and contiguous to said ring of second conductivity type.
Claim 4
Dependent Claim
39 words
A monolithically integrated semiconductor structure as set forth in claim 1 further including an output terminal connected to said collector zone, means for applying a control signal to said base zone and sensing means connected to said injection zone.
Claim 5
Dependent Claim
207 words
A monolithically integrated semiconductor memory comprising: a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type disposed on said semiconductor substrate, separating zones defining first and second portions of said semiconductor layer, each portion having a given width between first and second sides thereof, said separating zones including heavily doped semiconductor material of said second conductivity type, an inverting transistor disposed within each of said semiconductor layer portions, said transistor including a base zone of said first conductivity type and a collector zone of said second conductivity type disposed within said base zone, an injection zone of said first conductivity type disposed within each of said semiconductor layer portions and spaced from the base zone of said transistor by a given distance, the edge of said base zone and the edge of said injection zone facing each other within each of said layer portions extending from said first side to said second side, substantially the remaining edges of said base zones and of said injection zones being spaced from said separating zones by a predetermined distance, means for cross-coupling said inverting transistors to form a flip-flop circuit, and accessing means coupled to said injection zones and to said semiconductor layer portions.
Claim 6
Dependent Claim
207 words
A monolithically integrated semiconductor memory comprising: a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type disposed on said semiconductor substrate, separating zones defining first and second portions of said semiconductor layer, each portion having a given width between first and second sides thereof, said separating zones including heavily doped semiconductor material of said second conductivity type, an inverting transistor disposed within each of said semiconductor layer portions, said transistor including a base zone of said first conductivity type and a collector zone of said second conductivity type disposed within said base zone, an injection zone of said first conductivity type disposed within each of said semiconductor layer portions and spaced from the base zone of said transistor by a given distance, the edge of said base zone and the edge of said injection zone facing each other within each of said layer portions extending from said first side to said second side, substantially the remaining edges of said base zones and of said injection zones being spaced from said separating zones by a predetermined distance, means for cross-coupling said inverting transistors to form a flip-flop circuit, and accessing means coupled to said injection zones and to said semiconductor layer portions.
Claim 7
Dependent Claim
26 words
A monolithically integrated semiconductor memory as set forth in claim 4 wherein said accessing means includes a pair of bit lines connected to said injection zones.
Claim 8
Dependent Claim
26 words
A monolithically integrated semiconductor memory as set forth in claim 5 wherein said accessing means further includes an address line connected to said semiconductor layer portions.
Claim 9
Dependent Claim
26 words
A monolithically integrated semiconductor memory as set forth in claim 6 wherein said address line includes a heavily doped semiconductor zone of said second conductivity type.
Claim 10
Dependent Claim
17 words
A monolithically integrated semiconductor memory as set forth in claim 4 wherein cross-coupling means includes metal conductors.
Claim 11
Dependent Claim
30 words
A monolithically integrated semiconductor memory as set forth in claim 8 wherein said accessing means includes a pair of bit lines made of metal conductors connected to said injection zones.
Claim 12
Dependent Claim
164 words
A monolithically integrated semiconductor structure comprising: a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type disposed on said semiconductor substrate, a separating zone defining a portion of said semiconductor layer having a given width between first and second sides thereof, said separating zone including a ring of dielectric material, an inverting transistor disposed within said separating zone, said transistor including a base zone of said first conductivity type and a collector zone of said second conductivity type disposed within said base zone, and an injection zone of said first conductivity type disposed within said separating zone and spaced from the base zone of said transistor by a given distance, the edge of said base zone and the edge of said injection zone facing each other extending from said first side to said second side, substantially the remaining edges of said base zone and of said injection zone being spaced from said separating zone by a predetermined distance.
Claim 13
Dependent Claim
164 words
A monolithically integrated semiconductor structure comprising: a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type disposed on said semiconductor substrate, a separating zone defining a portion of said semiconductor layer having a given width between first and second sides thereof, said separating zone including a ring of dielectric material, an inverting transistor disposed within said separating zone, said transistor including a base zone of said first conductivity type and a collector zone of said second conductivity type disposed within said base zone, and an injection zone of said first conductivity type disposed within said separating zone and spaced from the base zone of said transistor by a given distance, the edge of said base zone and the edge of said injection zone facing each other extending from said first side to said second side, substantially the remaining edges of said base zone and of said injection zone being spaced from said separating zone by a predetermined distance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-30 | 1984-09-29 | 1985-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-30 | 1988-09-29 | 1989-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-30 | 1992-09-29 | 1993-03-31 | $7700.00 | Window Closed / Lapsed |