Patent US4258272A successfully refreshed from Google Patents.
US4258272A
Expired / Lapsed
US
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TTL to CMOS input buffer circuit
Assignee: National Semiconductor Corp
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Filing: 1979-03-19
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Granted: 1981-03-24
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Expires: 1999-03-19
Abstract
Abstract A TTL to CMOS input buffer integrated circuit having an input terminal for connection to an output terminal of a TTL device is disclosed. The buffer circuit includes a first CMOS inverter connected to the input terminal, including a first p-channel FET connected to a supply terminal and a first n-channel FET connected to a ground terminal, wherein the drain of the first p-channel FET is connected to the drain of the first n-channel FET at a first node; a second n-channel FET having its gate connected to the input terminal and its source connected to the ground terminal; a third n-channel FET having its gate connected to the first node, its drain connected to the supply terminal, and its source connected to the drain of the second n-channel FET at a second node for forcing the potential at the second node to be less than the potential at the first node by the amount of the threshold voltage of the third n-channel FET; and a second p-channel FET having its gate connected to the second node, its source connected to the first node, its drain connected to the ground terminal, and its substrate connected to the supply terminal, for reducing the rate at which the third n-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the n-channel FET's is greater than the threshold of the p-channel FET's.
Inventors
- 👤 Jen-Yen Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
236 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first CMOS inverter connected to the input terminal, including a first p-channel FET connected to the supply terminal and a first n-channel FET connected to the ground terminal, wherein the drain of the first p-channel FET is connected to the drain of the first n-channel FET at a first node; a second n-channel FET having its gate connected to the input terminal and its source connected to the ground terminal; a third n-channel FET having its gate connected to the first node, its drain connected to the supply terminal, and its source connected to the drain of the second n-channel FET at a second node for forcing the potential at the second node to be less than the potential at the first node by the amount of the threshold voltage of the third n-channel FET; and a second p-channel FET having its gate connected to the second node, its source connected to the first node, its drain connected to the ground terminal, and its substrate connected to the supply terminal for reducing the rate at which the third n-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the n-channel FET's is greater than the threshold of the p-channel FET's.
Claim 2
Dependent Claim
236 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first CMOS inverter connected to the input terminal, including a first p-channel FET connected to the supply terminal and a first n-channel FET connected to the ground terminal, wherein the drain of the first p-channel FET is connected to the drain of the first n-channel FET at a first node; a second n-channel FET having its gate connected to the input terminal and its source connected to the ground terminal; a third n-channel FET having its gate connected to the first node, its drain connected to the supply terminal, and its source connected to the drain of the second n-channel FET at a second node for forcing the potential at the second node to be less than the potential at the first node by the amount of the threshold voltage of the third n-channel FET; and a second p-channel FET having its gate connected to the second node, its source connected to the first node, its drain connected to the ground terminal, and its substrate connected to the supply terminal for reducing the rate at which the third n-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the n-channel FET's is greater than the threshold of the p-channel FET's.
Claim 3
Dependent Claim
65 words
A circuit according to claim 1, further comprising a second CMOS inverter connected to the second node, including a third p-channel FET having its source connected to the supply terminal, and a fourth n-channel FET having its source connected to the ground terminal and its drain connected to the drain of the third p-channel FET at a third node for providing a non-inverted output signal.
Claim 4
Dependent Claim
73 words
A circuit according to claim 2, further comprising a fourth p-channel FET having its gate connected to the third node, its source connected to the supply terminal and its drain connected to the second node for causing the potential at the second node to rise enough to terminate conduction in the third p-channel FET when the fourth n-channel FET has been rendered conductive, and for terminating any conduction through the third n-channel FET.
Claim 5
Dependent Claim
217 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first p-channel FET having its gate connected to the input terminal and its source connected to the supply terminal, wherein the drain of the first p-channel FET defines a first node; a first n-channel FET having its gate connected to the input terminal and its source connected to the ground terminal; a second n-channel FET having its gate connected to the first node, its drain connected to the supply terminal, and its source connected to the drain of the first n-channel FET at a second node for forcing the potential at the second node to be less than the potential at the first node by the amount of the threshold voltage of the second n-channel FET; and a second p-channel FET having its gate connected to the second node, its source connected to the first node, its drain connected to the ground terminal, and its substrate connected to the supply terminal for reducing the rate at which the second n-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the n-channel FET's is greater than the threshold of the p-channel FET's.
Claim 6
Dependent Claim
217 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first p-channel FET having its gate connected to the input terminal and its source connected to the supply terminal, wherein the drain of the first p-channel FET defines a first node; a first n-channel FET having its gate connected to the input terminal and its source connected to the ground terminal; a second n-channel FET having its gate connected to the first node, its drain connected to the supply terminal, and its source connected to the drain of the first n-channel FET at a second node for forcing the potential at the second node to be less than the potential at the first node by the amount of the threshold voltage of the second n-channel FET; and a second p-channel FET having its gate connected to the second node, its source connected to the first node, its drain connected to the ground terminal, and its substrate connected to the supply terminal for reducing the rate at which the second n-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the n-channel FET's is greater than the threshold of the p-channel FET's.
Claim 7
Dependent Claim
64 words
A circuit according to claim 4, further comprising a CMOS inverter connected to the second node, including a third p-channel FET having its source connected to the supply terminal, and a third n-channel FET having its source connected to the ground terminal and its drain connected to the drain of the third p-channel FET at a third node for providing a non-inverted output signal.
Claim 8
Dependent Claim
74 words
A circuit according to claim 5, further comprising a fourth p-channel FET having its gate connected to the third node, its source connected to the supply terminal and its drain connected to the second node for causing the potential at the second node to rise high enough to terminate conduction in the third p-channel FET when the third n-channel FET has been rendered conductive, and for terminating any conduction through the second n-channel FET.
Claim 9
Dependent Claim
235 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first CMOS inverter connected to the input terminal, including a first p-channel FET connected to the supply terminal and a first n-channel FET connected to the ground terminal, wherein the drain of the first p-channel FET is connected to the drain of the first n-channel at a first node; a second p-channel FET having its gate connected to the input terminal, and its source connected to the supply terminal; a third p-channel FET having its gate connected to the first node, its drain connected to the ground terminal, its substrate connected to the supply terminal, and its source connected to the drain of the second p-channel FET at a second node for forcing the potential at the second node to be greater than the potential at the first node by the amount of the threshold voltage of the third p-channel FET; and a second n-channel FET having its gate connected to the second node, its source connected to the first node, and its drain connected to the supply terminal, for reducing the rate at which the third p-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the p-channel FET's is greater than the threshold of the n-channel FET's.
Claim 10
Dependent Claim
235 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first CMOS inverter connected to the input terminal, including a first p-channel FET connected to the supply terminal and a first n-channel FET connected to the ground terminal, wherein the drain of the first p-channel FET is connected to the drain of the first n-channel at a first node; a second p-channel FET having its gate connected to the input terminal, and its source connected to the supply terminal; a third p-channel FET having its gate connected to the first node, its drain connected to the ground terminal, its substrate connected to the supply terminal, and its source connected to the drain of the second p-channel FET at a second node for forcing the potential at the second node to be greater than the potential at the first node by the amount of the threshold voltage of the third p-channel FET; and a second n-channel FET having its gate connected to the second node, its source connected to the first node, and its drain connected to the supply terminal, for reducing the rate at which the third p-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the p-channel FET's is greater than the threshold of the n-channel FET's.
Claim 11
Dependent Claim
65 words
A circuit according to claim 7, further comprising a second CMOS inverter connected to the second node, including a fourth p-channel FET having its source connected to the supply terminal, and a third n-channel FET having its source connected to the ground terminal and its drain connected to the drain of the fourth p-channel FET at a third node for providing a non-inverted output signal.
Claim 12
Dependent Claim
74 words
A circuit according to claim 6, further comprising a fourth n-channel FET having its gate connected to the third node, its source connected to the ground terminal and its drain connected to the second node for causing the potential at the second node to drop low enough to terminate conduction in the third n-channel FET when the fourth p-channel FET has been rendered conductive, and for terminating any conduction through the third p-channel FET.
Claim 13
Dependent Claim
217 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first n-channel FET having its gate connected to the input terminal, and its source connected to the ground terminal, wherein the drain of the first n-channel FET defines a first node; a first p-channel FET having its gate connected to the input terminal and its source connected to the supply terminal; a second p-channel FET having its gate connected to the first node, its drain connected to the ground terminal, its substrate connected to the supply terminal, and its source connected to the drain of the first p-channel FET at a second node for forcing the potential at the second node to be greater than the potential at the first node by the amount of the threshold voltage of the second p-channel FET; and a second n-channel FET having its gate connected to the second node, its source connected to the first node, and its drain connected to the supply terminal, for reducing the rate at which the second p-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the p-channel FET's is greater than the threshold of the n-channel FET's.
Claim 14
Dependent Claim
217 words
A TTL to CMOS input buffer integrated circuit, comprising an input terminal for connection to an output terminal of a TTL device; a supply terminal; a ground terminal; a first n-channel FET having its gate connected to the input terminal, and its source connected to the ground terminal, wherein the drain of the first n-channel FET defines a first node; a first p-channel FET having its gate connected to the input terminal and its source connected to the supply terminal; a second p-channel FET having its gate connected to the first node, its drain connected to the ground terminal, its substrate connected to the supply terminal, and its source connected to the drain of the first p-channel FET at a second node for forcing the potential at the second node to be greater than the potential at the first node by the amount of the threshold voltage of the second p-channel FET; and a second n-channel FET having its gate connected to the second node, its source connected to the first node, and its drain connected to the supply terminal, for reducing the rate at which the second p-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the p-channel FET's is greater than the threshold of the n-channel FET's.
Claim 15
Dependent Claim
64 words
A circuit according to claim 10, further comprising a CMOS inverter connected to the second node, including a third p-channel FET having its source connected to the supply terminal, and a third n-channel FET having its source connected to the ground terminal and its drain connected to the drain of the third p-channel FET at a third node for providing a non-inverted output signal.
Claim 16
Dependent Claim
74 words
A circuit according to claim 11, further comprising a fourth n-channel FET having its gate connected to the third node, its source connected to the ground terminal and its drain connected to the second node for causing the potential at the second node to drop low enough to terminate conduction in the third n-channel FET when the third p-channel FET has been rendered conductive, and for terminating any conduction through the second p-channel FET.
References Cited (Backward Citations)
US3676700A
Cited
US4031409A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-23 | 1984-09-22 | 1985-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-23 | 1988-09-22 | 1989-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-23 | 1992-09-22 | 1993-03-24 | $7700.00 | Window Closed / Lapsed |