US4031409A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal converter circuit
Assignee: Hitachi Ltd
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Filing: 1976-05-26
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Granted: 1977-06-21
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Expires: 1996-05-26
Abstract
Abstract A signal converter circuit for converting a binary signal delivered from a bipolar transistor logic circuit into another binary signal adapted for application to a MIS transistor logic circuit. The converter circuit comprises first, second and third stages; the first stage includes a source follower circuit, the second stage includes a series connection of a pair of parallel-connected MIS FETs and a switching MIS FET, and the third stage includes an inverter circuit. The output of the third stage is fed back to the gate of one of the pair of MIS FETs in the second stage so that the converter output has binary levels acceptable to a MIS logic circuit.
Inventors
- 👤 Shunji Shimada
- 👤 Harumi Wakimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
214 words
A signal converter circuit comprising: a first stage including a source follower circuit having a MIS FET and a first load connected to the source of the MIS FET, the gate of said MIS FET being arranged for reception of an input to the signal converter cicuit; a second stage including a pair of MIS FETs having their drains connected to each other and their sources connected to each other, a switching MIS FET having its drain connected to the sources of said pair of MIS FETs and its gate connected to the output of said source follower circuit, and a second load connected to the drains of said pair of MIS FETs; and a third stage including an inverter circuit having a MIS FET and a third load connected to the drain of the MIS FET, the gate of the MIS FET in said third stage being connected to the drains of said pair of MIS FETs in said second stage; the gate of one of said pair of MIS FETs in said second stage being connected to the gate of the MIS FET in said first stage while the gate of the other of said pair of MIS FETs being connected to the drain of the MIS FET in said third stage.
Claim 2
Dependent Claim
214 words
A signal converter circuit comprising: a first stage including a source follower circuit having a MIS FET and a first load connected to the source of the MIS FET, the gate of said MIS FET being arranged for reception of an input to the signal converter cicuit; a second stage including a pair of MIS FETs having their drains connected to each other and their sources connected to each other, a switching MIS FET having its drain connected to the sources of said pair of MIS FETs and its gate connected to the output of said source follower circuit, and a second load connected to the drains of said pair of MIS FETs; and a third stage including an inverter circuit having a MIS FET and a third load connected to the drain of the MIS FET, the gate of the MIS FET in said third stage being connected to the drains of said pair of MIS FETs in said second stage; the gate of one of said pair of MIS FETs in said second stage being connected to the gate of the MIS FET in said first stage while the gate of the other of said pair of MIS FETs being connected to the drain of the MIS FET in said third stage.
Claim 3
Dependent Claim
79 words
A signal converter circuit according to claim 1, in which each of said second and third loads are constituted by a depletion type MIS FET having its gate and source connected to each other, the source of said second load MIS FET being connected to the drains of said pair of MIS FETs in said second stage while the source of the third load MIS FET being connected to the drain of the MIS FET in said third stage.
Claim 4
Dependent Claim
53 words
A signal converter circuit according to claim 2, in which said first load is constituted by an enhancement type MIS FET having its drain connected to the source of the MIS FET in said first stage and its gate connected to the drains of said pair of MIS FETs in said second stage.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |