Patent US1770805A successfully refreshed from Google Patents.
US3859641A
Expired / Lapsed
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Dynamic buffer circuit
Assignee: AT&T Inc
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Filing: 1973-12-10
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Granted: 1975-01-07
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Expires: 1993-12-10
Abstract
Abstract An input data buffer circuit, which includes six field effect transistors, is utilized in combination with a dynamic memory in order to widen the operating margins of the memory system. The buffer circuit is fabricated on the same integrated circuit chip as the memory, so that the electrical characteristics of the transistors of the buffer circuit and of the memory will be essentially identical. The levels of the output signals of the buffer circuit are relatively independent of random variations in levels of input signals because the levels of the output signals are primarily a function of the magnitude of the common power supply used by the buffer circuit and the memory, the electrical characteristics of the transistors of the buffer circuit and the memory, and the internal and external signals utilized by the memory.
Inventors
- 👤 Donald Gordon Clemons
- 👤 James Howard Vogelsong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:40
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/405; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
216 words
A buffer circuit comprising: first circuit means including a control port, a first port and a second port, said first means being adapted to selectively appear as an open or short circuit such that a voltage level applied to the first port is either isolated from or coupled to the second port; second circuit means coupled to the control port of the first means for selectively causing the first means to appear as a short circuit; third circuit means coupled to the control port of the first means for selectively causing the first means to appear as an open circuit; said third means including a control port; fourth circuit means coupled to the control port of the third circuit means for selectively controlling when the third circuit means causes the first circuit means to appear as an open circuit; fifth circuit means including a control port, a first port, and a second port; the first port of the fifth circuit means being coupled to the second port of the first circuit means; and a sixth circuit means coupled to the control ports of the third and fifth circuit means, said sixth circuit means being adapted to selectively allow signal information applied thereto to be applied to the control ports of the third and fifth circuit means.
Claim 2
Dependent Claim
216 words
A buffer circuit comprising: first circuit means including a control port, a first port and a second port, said first means being adapted to selectively appear as an open or short circuit such that a voltage level applied to the first port is either isolated from or coupled to the second port; second circuit means coupled to the control port of the first means for selectively causing the first means to appear as a short circuit; third circuit means coupled to the control port of the first means for selectively causing the first means to appear as an open circuit; said third means including a control port; fourth circuit means coupled to the control port of the third circuit means for selectively controlling when the third circuit means causes the first circuit means to appear as an open circuit; fifth circuit means including a control port, a first port, and a second port; the first port of the fifth circuit means being coupled to the second port of the first circuit means; and a sixth circuit means coupled to the control ports of the third and fifth circuit means, said sixth circuit means being adapted to selectively allow signal information applied thereto to be applied to the control ports of the third and fifth circuit means.
Claim 3
Dependent Claim
96 words
A buffer circuit comprising six insulated gate field effect transistors T1-T6, each of the transistors comprising a first terminal, a second terminal, and a control terminal; the control terminal of T1 being coupled to the second terminal of T3 and the first terminal of T4; the second terminal of T1 being coupled to the first terminal of T6; the control terminal of T3 being coupled to the second terminal of T2, the control terminal of T6, and the second terminal of T5; and the control terminal of T2 being coupled to the control terminal of T4.
Claim 4
Dependent Claim
96 words
A buffer circuit comprising six insulated gate field effect transistors T1-T6, each of the transistors comprising a first terminal, a second terminal, and a control terminal; the control terminal of T1 being coupled to the second terminal of T3 and the first terminal of T4; the second terminal of T1 being coupled to the first terminal of T6; the control terminal of T3 being coupled to the second terminal of T2, the control terminal of T6, and the second terminal of T5; and the control terminal of T2 being coupled to the control terminal of T4.
Claim 5
Dependent Claim
28 words
The apparatus of claim 2 wherein: the control terminals of T2 and T5 serve as input terminals and the first terminal of T6 serves as the output terminal.
References Cited (Backward Citations)
US3599180A
Cited
US3593037A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |