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US4256532A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making a silicon mask

Assignee: International Business Machines Corp
•
Filing: 1978-12-04
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Granted: 1981-03-17
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Expires: 1998-12-04
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Abstract

Abstract In the fabrication of semiconductor integrated circuits, a method is provided for forming a self-supporting silicon mask and a further method is provided for utiliziing such a self-supporting separable silicon mask to perform various masking steps in the integrated circuit fabrication. The mask is formed by forming, at a surface of a planar silicon substrate, a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath the layer, applying to selected portions of the other surface of the substrate an etchant which preferentially etches silicon having lower concentrations of conductivity-determining impurities to thus etch out preferentially selected portions of the substrate to form at least one recess extending through the substrate to said silicon layer, and then etching from the surface of said silicon layer opposite the substrate recess to form patterns of openings extending through the silicon layer to said substrate recess. The seperable self-supporting silicon mask thus formed is then placed on the surface of an integrated semiconductor circuit member so that the opposite surface of the silicon layer interfaces with the integrated circuit member surface. Then, the masked semiconductor member may be subjectd to any conventional integrated circuit fabrication step which alters the characteristics of the portions of said member surface exposed in said pattern of mask openings; such fabrication steps include introduction of impurities, etching as well as lift-off deposition of metallic and non-metallic patterns. Upon the completion of the step or steps, the self-supporting silicon mask is separated from the integrated circuit member.

Inventors

  • 👤 Ingrid E. Magdo
  • 👤 Steven Magdo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 12:40
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/20; H; H10; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10P76/00; H10P76/40; H10P76/405; H10P76/408; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/924; Y10S438/928; Y10S438/942; Y10S438/944; Y10T; Y10T428/00; Y10T428/24; Y10T428/24273; Y10T428/24298; Y10T428/24322; Y10T428/24479

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 158 words
A method for fabricating a self-supporting silicon mask comprising: forming at a surface of a planar silicon substrate a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath said layer, forming a masking layer on the surface of said silicon layer, said masking layer comprising a layer of chemical vapor deposited silicon dioxide and an overlying layer of silicon nitride in contact with said silicon layer surface, applying to selected portions of the other surface of said substrate an etchant comprising ethylene diamine, pyrocatechol and water which preferentially etches silicon having lower concentrations of conductivity-determining impurities to preferentially etch out the entire thickness of selected portions of said substrate to form at least one recess extending completely through said substrate to said silicon layer, each said recess having a lateral dimension in the order of 12,500 microns and said silicon remaining in said recesses having a thickness in the order of 5 microns, and
Claim 2
Independent Claim 158 words
A method for fabricating a self-supporting silicon mask comprising: forming at a surface of a planar silicon substrate a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath said layer, forming a masking layer on the surface of said silicon layer, said masking layer comprising a layer of chemical vapor deposited silicon dioxide and an overlying layer of silicon nitride in contact with said silicon layer surface, applying to selected portions of the other surface of said substrate an etchant comprising ethylene diamine, pyrocatechol and water which preferentially etches silicon having lower concentrations of conductivity-determining impurities to preferentially etch out the entire thickness of selected portions of said substrate to form at least one recess extending completely through said substrate to said silicon layer, each said recess having a lateral dimension in the order of 12,500 microns and said silicon remaining in said recesses having a thickness in the order of 5 microns, and
Claim 3
Dependent Claim 34 words
forming a pattern of apertures through said masking layer and etching said silicon layer through said apertures to form a corresponding pattern of openings through said silicon layer to at least one substrate recess.
Claim 4
Dependent Claim 34 words
forming a pattern of apertures through said masking layer and etching said silicon layer through said apertures to form a corresponding pattern of openings through said silicon layer to at least one substrate recess.
Claim 5
Dependent Claim 35 words
The method of claim 1 wherein said selected portions of said substrate are preferentially etched out to form a plurality of recesses separated from each other and supported by the unetched portions of said substrate.
Claim 6
Dependent Claim 24 words
The method of claim 2 wherein said etching of the silicon layer to form said pattern of openings is carried out by sputter etching.
Claim 7
Dependent Claim 12 words
The method of claim 3 wherein said sputter etching utilizes reactive ions.
Claim 8
Dependent Claim 16 words
The method of claim 2 wherein said mask recesses have minimum lateral dimensions of 1250 microns.
Claim 9
Dependent Claim 28 words
The method of claim 5 wherein said unetched portions of said mask are at least twenty-five times as thick as said silicon layer remaining in said mask recesses.
Claim 10
Dependent Claim 21 words
The method of claim 1 wherein said silicon substrate surface has a 100 crystallographic orientation, and said conductivity-determining impurity is boron.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-03-16 1984-09-15 1985-03-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-03-16 1988-09-15 1989-03-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-03-16 1992-09-15 1993-03-17 $7700.00 Window Closed / Lapsed

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