High reverse voltage semiconductor device with fast recovery time with central depression

Claim 2

A high voltage semiconductor device which at least includes a P-I-N diode comprising a monocrystalline wafer of semiconductor material having first and second spaced, generally parallel surfaces; said wafer having a first region of one of the conductivity types extending from said first surface; a second and central region ajoining one side of said first region and being of the other of the conductivity types and having a relatively high resistivity; and a third region of said other of the conductivity types which adjoins the opposite side of said central region and extends to said second surface; said third region having a central depression therein; said third region generally following the contour of said central depression and terminating on said second surface; said first, second and third regions having a common peripheral edge, whereby electric field equipotential lines during reverse biasing of said P-I-N diode are relatively widely distributed around said edge of said wafer to decrease the local field stress on said edge of said device.

Claim 3

The device of claim 1 wherein the rim of said wafer is tapered in a direction to reduce the area at the top of said third region of said wafer relative to the bottom of said first region.

Claim 4

The device of claim 2 wherein said taper has an angle substantially greater than 6° relative to the plane of said wafer and wherein said device has a reverse voltage withstand ability in excess of 1500 volts.

Claim 5

The device of claim 1, 2 or 3 which further includes first and second contact means connected to said first and third regions respectively.

Claim 6

The device of claim 4 wherein said first region is of P type and wherein said central region and upper regions are of the N and N+ types respectively.

Claim 7

The device of claim 1, 2 or 3 wherein said central region has a thickness beneath said central depression of less than about 10 mils.

Claim 8

The device of claim 3 wherein said taper has an angle of about 45°.

Claim 9

A high voltage P-I-N diode comprising a monocrystalline wafer of semiconductor material having generally parallel first and second end surfaces; said first end surface having a central depression therein; a first relatively high conductivity region in said wafer of one of the conductivity types extending from the surface of said central depression; a second relatively low conductivity region of said one of said conductivity types adjoining said first region and extending for a predetermined distance away from said first region and extending to the outer edge of said wafer; and a third conductivity region of the other of said conductivity types extending from said second end surface and adjoining said second conductivity region; said first and second regions meeting one another on said first end surface; said second and third regions meeting one another on the peripheral edge of said wafer, whereby electric field equipotential lines during reverse biasing of said P-I-N diode are relatively widely distributed around said peripheral edge of said wafer to decrease the local field stress on said edge of said wafer.

Claim 10

A high voltage P-I-N diode comprising a monocrystalline wafer of semiconductor material having generally parallel first and second end surfaces; said first end surface having a central depression therein; a first relatively high conductivity region in said wafer of one of the conductivity types extending from the surface of said central depression; a second relatively low conductivity region of said one of said conductivity types adjoining said first region and extending for a predetermined distance away from said first region and extending to the outer edge of said wafer; and a third conductivity region of the other of said conductivity types extending from said second end surface and adjoining said second conductivity region; said first and second regions meeting one another on said first end surface; said second and third regions meeting one another on the peripheral edge of said wafer, whereby electric field equipotential lines during reverse biasing of said P-I-N diode are relatively widely distributed around said peripheral edge of said wafer to decrease the local field stress on said edge of said wafer.

Claim 11

The diode of claim 8 wherein said peripheral edge of said wafer is tapered in a direction to reduce the area of said first end surface relative to said second end surface.

Claim 12

The diode of claim 9 wherein said taper has an angle substantially greater than 6° relative to the plane of said wafer and wherein said diode has a reverse voltage withstand ability in excess of 1500 volts.

Claim 13

The diode of claim 8 wherein said first region is of the N+ type, said second region is of the N type, and said third region is of the P type.

Claim 14

The diode of claim 9 wherein the central region beneath said central depression has a thickness of less than about 10 mils.

Claim 15

The diode of claim 9 wherein said taper has an angle of about 45°.

Claim 16

The device of claim 4 wherein said central region has a thickness beneath said central depression of less than about 10 mils.