Patent US4255672A successfully refreshed from Google Patents.
US4255672A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Large scale semiconductor integrated circuit device
Assignee: Fujitsu Ltd
•
Filing: 1978-12-28
•
Granted: 1981-03-10
•
Expires: 1998-12-28
Abstract
Abstract A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on the substrate surface. Groups of these emitter coupled circuits are disposed in the form of arrays with circuits of several groups handling larger power than those of other groups, and resistance values in the emitter coupled circuits of the different groups are selected in accordance with the position and arrangement of each group to compensate for any potential variation between that group and the power supply and ground terminals between the groups and respective input/output terminals. Large scale transistors are provided for outputting the emitter-follower circuits. These groups contain the emitter coupled circuits, and are connected to the input/output terminals by the double metallic wiring layer.
Inventors
- 👤 Kenichi Ohno
- 👤 Tohru Hosomizu
- 👤 Rokutaro Ogawa
- 👤 Mitsuhisa Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:52
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/901
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
125 words
An LSI chip comprising: a semiconductor substrate having a planar surface; transistors and resistors formed with selected patterns in said surface; metallic layers formed on said substrate comprising systems for connecting said transistors and resistors and for distributing supply and ground potentials; macros comprising logic circuits, said macros being disposed in at least one array on said surface, and said logic circuits selectively comprising said transistors, resistors and metallic layers; input/output terminal pads provided on said surface near the periphery of said macro array(s), said input/output pads comprising terminal pads for said supply and ground potentials; said resistors forming said logic circuits being selected for compensating voltage variations along said metallic layers comprising said supply and ground potential distribution systems connected to said logic circuits.
Claim 2
Dependent Claim
125 words
An LSI chip comprising: a semiconductor substrate having a planar surface; transistors and resistors formed with selected patterns in said surface; metallic layers formed on said substrate comprising systems for connecting said transistors and resistors and for distributing supply and ground potentials; macros comprising logic circuits, said macros being disposed in at least one array on said surface, and said logic circuits selectively comprising said transistors, resistors and metallic layers; input/output terminal pads provided on said surface near the periphery of said macro array(s), said input/output pads comprising terminal pads for said supply and ground potentials; said resistors forming said logic circuits being selected for compensating voltage variations along said metallic layers comprising said supply and ground potential distribution systems connected to said logic circuits.
Claim 3
Dependent Claim
32 words
The LSI chip of claim 1, said resistors forming said logic circuits being selectively determined in accordance with distances between the corresponding macro and said supply and ground potential terminal pads, respectively.
Claim 4
Dependent Claim
35 words
The LSI chip of claim 1, said macros comprising said logic circuits being selectively grouped in accordance with said distances and wherein corresponding resistors in the macros of each group have the same resistance values.
Claim 5
Dependent Claim
11 words
The LSI chip of claim 3, said grouping comprising five groups.
Claim 6
Dependent Claim
49 words
The LSI chip of claim 3, said chip comprising means for providing at least one reference voltage for said macros, and said resistors forming said logic circuits being selectively determined so that the level of at least one selected reference voltage in each of said groups is the same.
Claim 7
Dependent Claim
61 words
The LSI chip of claim 3, said logic circuits comprising emitter coupled logic circuits, said emitter coupled logic circuits having at least one low level output (V OL ) at least one low level output being the same in each of said groups of logic circuits, as a result of said resistors forming said logic circuits being selectively determined the same.
Claim 8
Dependent Claim
26 words
The chip of claim 5, said logic circuits comprising emitter coupled logic circuits, and said selected reference voltage comprising a reference switching voltage (V REF ).
Claim 9
Dependent Claim
46 words
The chips of claim 6 comprising at least two of said low level outputs (V OR , V NOR ), at least one of said low level outputs being the same in each said logic circuit as a result of said selective determination of said resistors.
References Cited (Backward Citations)
US3225261A
Cited
US3539876A
Cited
US3555443A
Cited
US3817797A
Cited
US3638202A
Cited
US3621562A
Cited
US3689803A
Cited
US3747078A
Cited
US3808475A
Cited
US3909636A
Cited
US3866066A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-09 | 1984-09-08 | 1985-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-09 | 1988-09-08 | 1989-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-09 | 1992-09-08 | 1993-03-10 | $7700.00 | Window Closed / Lapsed |