US3689803A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit structure having a unique surface metallization layout
Assignee: International Business Machines Corp
•
Filing: 1971-03-30
•
Granted: 1972-09-05
•
Expires: 1991-03-30
Abstract
Abstract A planar monolithic integrated circuit chip containing an isolation region of one conductivity type extending completely around the edge or periphery of the chip in order to insure that there are no exposed P-N junctions on an edge surface of the chip. Such an isolation region extends for at least a minimum distance from the edge of the chip, said distance being determined so as to minimize the risk of any edge defects in the chip resulting from dicing and handling from extending beyond the isolation region into the body of the chip. An insulative layer over the planar surface of the chip supports a metallization pattern for interconnecting the devices in the integrated circuit and for distributing a plurality of voltage supplys at different levels to the devices. The metallization pattern is arranged so that only metallization connected to the voltage supply at the same level as the peripheral isolation region is located on the portion of the insulative layer between the chip edge and the minimum distance of the isolation junction from the edge.
Inventors
- 👤 Theodore H Baker
- 👤 Daniel Tuman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:23
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/901; H10D89/00; H10D89/10; H10P; H10P95/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
223 words
In a plAnar semiconductor integrated circuit chip structure comprising a planar surface from which a plurality of regions of different conductivity types extend into the chip to provide the active and passive devices of the circuit, a layer of insulative material covering said surface, a plurality of electrical contacts extending through openings in said insulative layer respectively to said regions, and a metallization pattern formed on said insulative layer respectively connecting each of a plurality of voltage supplies having different levels to different regions through said contacts, the improvement comprising the combination of: an isolation region of one conductivity type extending from said planar surface around the edge of the chip and regions of opposite type conductivity abutting said isolation region and more inward from said edge than said isolation region to form a P-N isolation junction surrounding the devices in the circuit, said isolation junctions being spaced from said edge by at least a predetermined minimum distance, means for applying the level of one of said plurality of voltage supplies to said isolation region, and a metallization pattern on said insulative layer wherein only metallization connected to the voltage supply at the same voltage level as said isolation region is located on the portion of the insulative layer between said edge and said minimum distance of said isolation junction from said edge.
Claim 2
Dependent Claim
223 words
In a plAnar semiconductor integrated circuit chip structure comprising a planar surface from which a plurality of regions of different conductivity types extend into the chip to provide the active and passive devices of the circuit, a layer of insulative material covering said surface, a plurality of electrical contacts extending through openings in said insulative layer respectively to said regions, and a metallization pattern formed on said insulative layer respectively connecting each of a plurality of voltage supplies having different levels to different regions through said contacts, the improvement comprising the combination of: an isolation region of one conductivity type extending from said planar surface around the edge of the chip and regions of opposite type conductivity abutting said isolation region and more inward from said edge than said isolation region to form a P-N isolation junction surrounding the devices in the circuit, said isolation junctions being spaced from said edge by at least a predetermined minimum distance, means for applying the level of one of said plurality of voltage supplies to said isolation region, and a metallization pattern on said insulative layer wherein only metallization connected to the voltage supply at the same voltage level as said isolation region is located on the portion of the insulative layer between said edge and said minimum distance of said isolation junction from said edge.
Claim 3
Dependent Claim
43 words
The integrated circuit chip of claim 1 wherein said chip comprises a semiconductor substrate of the same conductivity type as said isolation region and an epitaxial layer having said planar surface on said substrate, and said isolation region is in said epitaxial layer.
Claim 4
Dependent Claim
38 words
The integrated circuit chip of claim 1 wherein said metallization at the same voltage level as the isolation is arranged on said edge portion of the insulative layer as at least one bus bar along said edge portion.
Claim 5
Dependent Claim
27 words
The integrated circuit chip of claim 3 wherein said at least one bus bar is a pair of bus bars around the edge of said insulative layer.
Claim 6
Dependent Claim
44 words
The integrated circuit chip of claim 1 wherein said chip is a master slice structure having an excess number of said active and passive devices, the selected integrated circuit being determined by the metallization pattern and the number and disposition of said electrical contacts.
Claim 7
Dependent Claim
37 words
The integrated circuit of claim 5 wherein said metallization at the same voltage level as the isolation is arranged on said edge portion of the insulative layer as at least one bus bar along said edge portion.
Claim 8
Dependent Claim
26 words
The integrated circuit of claim 6 wherein said at least one bus bar is a pair of bus bars around the edge of said insulative layer.
Claim 9
Dependent Claim
154 words
The integrated circuit of claim 3 wherein the metallization is arranged so as to include a plurality of lines spaced inwardly of said bus bar and each other and disposed in the same direction as said bus bar, said plurality of regions includes an array of regions of selected conductivity type and resistivity disposed substantially normal to the edge of the chip and passing under said plurality of spaced metallization lines, each of regions having one end proximate said bus bar and another end inwardly of said spaced metallization lines, and a plurality of said arrayed regions being selectively connected to said bus bar by electrical contacts through the insulative layer to the proximate ends of said regions and having electrical contacts to their other ends whereby underpass paths of fixed resistance from the bus bar are provided to connect the voltage level of the bus bar to inward portions of the chip surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-05 | 1976-03-06 | 1976-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-05 | 1980-03-06 | 1980-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-05 | 1984-03-06 | 1984-09-05 | $7700.00 | Window Closed / Lapsed |