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US4253182A
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US
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Optimization of error detection and correction circuit
Assignee: Unisys Corp
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Filing: 1979-04-09
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Granted: 1981-02-24
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Expires: 1999-04-09
Abstract
Abstract There is provided an error detection and correction circuit which is optimized in terms of the operation, part count and the like. This invention includes parity generator circuitry to generate parity signals in accordance with a variation of the Hamming Code in response to the application of a plurality of input data bits. The parity signals are applied to a memory bus during a write cycle. During a read cycle, the parity generators produce a parity error signal, if appropriate, to indicate an error in parity. The error correction circuit receives the data bits from the memory (or memory bus) along with the parity error signals generated by the parity generator circuit portion. The data signals and parity error signals are gated together and supplied to Exclusive-OR gates. If an error is indicated by the level of the input signal, the Exclusive-OR gate converts the signal thereby correcting the erroneous data bit. The circuit further provides means for checking the parity of the parity bits, per se, thereby to provide a double bit error check.
Inventors
- 👤 Brewster J. Porcella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:21
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/19; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
107 words
An error detection circuit comprising: parity generator circuitry; input means for supplying input signals to said parity generator circuitry; control means for controlling whether said parity generator circuitry is in a read mode and/or a write mode; storage means; said parity generator circuitry producing parity bits as a function of the applied input signals and supplying said parity bits to said storage means when said parity generator circuitry is in a write mode; said parity generator circuitry producing parity error bits as a function of the applied input signals and said parity bits in said storage means when said parity generator circuitry is in a read mode.
Claim 2
Dependent Claim
107 words
An error detection circuit comprising: parity generator circuitry; input means for supplying input signals to said parity generator circuitry; control means for controlling whether said parity generator circuitry is in a read mode and/or a write mode; storage means; said parity generator circuitry producing parity bits as a function of the applied input signals and supplying said parity bits to said storage means when said parity generator circuitry is in a write mode; said parity generator circuitry producing parity error bits as a function of the applied input signals and said parity bits in said storage means when said parity generator circuitry is in a read mode.
Claim 3
Dependent Claim
79 words
The error detection circuit recited in claim 1 including error correction means comprising: logic circuitry connected to receive said input signals from said input means and said parity error bits from said parity generator circuitry and to produce output signals representative of said input signals; said logic circuitry operative to selectively alter the logic state of the input signals as a function of the parity error bit applied thereto whereby an error condition at said input signals is corrected.
Claim 4
Dependent Claim
24 words
The error detection and correction circuit recited in claim 2 including: driver means connecting the output of said logic circuitry to a memory bus.
Claim 5
Dependent Claim
54 words
The error detection and correction circuit recited in claim 2 wherein: said logic circuitry includes a plurality of NAND gates connected to said parity generator circuitry to receive said parity error bits therefrom; and a plurality of Exclusive-OR gates connected to receive said input signals and the output signals produced by said NAND gates.
Claim 6
Dependent Claim
24 words
The error detection and correction circuits recited in claim 4 including: inverter means connected to said Exclusive-OR gates for supplying said input signals thereto.
Claim 7
Dependent Claim
39 words
The error detection circuit recited in claim 1 wherein: said parity generator circuitry comprises a plurality of parity generator trees; and said control means includes driver means respectively connected to one input of each of said parity generator trees.
Claim 8
Dependent Claim
41 words
The error detection circuit recited in claim 6 wherein: said driver means selectively applies a logic level to said parity generator tree in the write mode and is, effectively, disabled in the read mode in response to a read/write mode signal.
Claim 9
Dependent Claim
16 words
The error detection circuit recited in claim 1 wherein, said storage means includes a memory bus.
Claim 10
Dependent Claim
29 words
The error detection circuit recited in claim 2 wherein, said input signals are supplied to said storage means from said input means before being supplied to said logic circuitry.
Claim 11
Dependent Claim
17 words
The error detection circuit recited in claim 1 wherein, said input means comprises a digital computer system.
Claim 12
Dependent Claim
34 words
The error detection circuit recited in claim 1 including, logic means connected to receive said parity error signals produced by said parity generator circuitry to produce a signal which indicates an error in parity.
Claim 13
Dependent Claim
57 words
The error detection circuit recited in claim 11 including, parity generator means connected to receive said parity error signals produced by said parity generator circuitry, and gate means connected to receive an output signal from said parity generator means and the signal from said logic means to produce an output signal which indicates a multiple bit error.
Claim 14
Dependent Claim
31 words
The error detection circuit recited in claim 1 wherein, said parity generator circuitry is connected to receive input signals and parity bits in accordance with the code shown in FIG. 4.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-24 | 1984-08-25 | 1985-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-24 | 1988-08-25 | 1989-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-24 | 1992-08-25 | 1993-02-24 | $7700.00 | Window Closed / Lapsed |