← Back to Patent Explorer
US3751646A Expired / Lapsed US ⏱️ 0.0 years remaining

Error detection and correction for data processing systems

Assignee: International Business Machines Corp
•
Filing: 1971-12-22
•
Granted: 1973-08-07
•
Expires: 1991-12-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An error detecting and correcting system is provided for a unit having an essentially subordinate structure, such as a function unit of a computer. Correct output signals are assumed for the unit and, accordingly, check bits are formed as a function of the output signals of the unit. These bits are stored with a control word associated with each operation. As the operation is being executed, the check bits are regenerated from the output signals of the function unit and are subsequently compared with the correct check bits previously stored. Non-concurrence of the check bits indicates that an error may have occurred in the unit.

Inventors

  • 👤 H Geng
  • 👤 V Goetze
  • 👤 J Hajdu
  • 👤 P Skuin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 15:54
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H; H03; H03M; H03M13/00; H03M13/03; H03M13/05

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 81 words
In an error detection system for a functional unit which responds to information within a data processing system; means for storing at least one check bit indicative of the error free operation of said functional unit in association with said information; means for regenerating the check bits from the output of said functional unit after operating in response to said information; means for comparing the stored check bits with the regenerated check bits thereby detecting the errors indicated by any noncomparison.
Claim 2
Dependent Claim 81 words
In an error detection system for a functional unit which responds to information within a data processing system; means for storing at least one check bit indicative of the error free operation of said functional unit in association with said information; means for regenerating the check bits from the output of said functional unit after operating in response to said information; means for comparing the stored check bits with the regenerated check bits thereby detecting the errors indicated by any noncomparison.
Claim 3
Dependent Claim 30 words
A system in accordance with claim 1, wherein said functional unit is the operation decoder and said information is the operation code of the control of a data processing system.
Claim 4
Dependent Claim 39 words
A system in accordance with claim 2, wherein said means for storing at least one check bit comprises a control word storage where said at least one check bit is stored in a field of the associated control word.
Claim 5
Dependent Claim 37 words
A system in accordance with claim 2, wherein said storage means includes a separate storage for said at least one check bit; means for fetching said check bit(s) together with said operation code acting as an address.
Claim 6
Dependent Claim 79 words
A system according to claim 1, wherein said functional unit has its output lines subdivided into groups, at least one check being provided for each group and the check bits of each group being separately stored in said means for storing a plurality of said regenerating means are provided one for each of said groups and a plurality of said comparison means are provided one for each of said groups so that errors can be detected by said non-comparison.
Claim 7
Dependent Claim 29 words
A system in accordance with claim 3, wherein a parity bit is generated from the control word which includes said at least one check bit and is then stored.
Claim 8
Dependent Claim 32 words
A system in accordance with claim 6, wherein said parity bit is regenerated by said regenerating means from the control word and is compared in said comparison unit said stored parity bit.
Claim 9
Dependent Claim 66 words
A system according to claim 6, wherein the control word has its outputs arranged in groups, a parity bit being provided for each group and being separately stored, a plurality of said regenerating means are provided one for each of said groups and a plurality of said comparison means are provided one for each of said groups so that errors can be detected by said non-comparison.

References Cited (Backward Citations)

US3218612A Cited
US3231858A Cited
US3387262A Cited
US3478313A Cited
US3531631A Cited
US3599146A Cited
US3573728A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-08-06 1977-02-05 1977-08-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-08-06 1981-02-05 1981-08-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-08-06 1985-02-05 1985-08-07 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag